Abstract: One embodiment of a computer-implemented method for processing ray tracing operations in parallel includes receiving a plurality of rays and a corresponding set of material shading instructions for each ray included in the plurality of rays for processing, wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment, and each corresponding set of material shading instructions is based at least in part on one or more material properties associated with at least one surface of at least one object included in the 3D environment; assigning each ray included in the plurality of rays to a different processing core included in a plurality of processing cores; and for each ray included in the plurality of rays, causing the processing core assigned to the ray to execute the corresponding set of material shading instructions on the ray to generate a color.

Abstract: One embodiment of a computer-implemented method for decompressing a compressed texture block includes identifying a first texel included in a plurality of texels, wherein the plurality of texels forms at least a portion of a compressed texture block; determining a first location within the compressed texel block that corresponds to the first texel; and extracting the first texel from the first location without decompressing any of the other texels included in the plurality of texels.

Abstract: One embodiment of a computer-implemented method for compiling a material graph into a set of instructions for execution within an execution unit includes receiving a first material graph having a plurality of nodes, wherein each node included in the plurality of nodes represents a different surface property of a material; parsing the material graph to generate an expression tree that includes one or more expressions for each node included in the plurality of nodes; and generating a set of byte code instructions corresponding to the material graph based on the expression tree, wherein the byte code instructions are executable by a plurality of processing cores included within the execution unit.

Abstract: One embodiment of a computer-implemented method for processing data within a fixed-function pipeline included in an execution unit includes receiving a first input from a first processing unit, wherein the first input corresponds to a first fixed-function; executing the first fixed-function on the first input to generate a first output, wherein the first fixed-function is executed on the first input prior to executing the first fixed-function on one or more inputs received from a plurality of processing cores that are processing a plurality of rays, and wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment; and transmitting the first output to the first processing unit for further processing.

Abstract: One embodiment of a computer-implemented method for processing ray tracing operations in parallel includes receiving a plurality of rays and a corresponding set of importance sampling instructions for each ray included in the plurality of rays for processing, wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment, and each corresponding set of importance sampling instruction is based at least in part on one or more material properties associated with at least one surface of at least one object included in the 3D environment; assigning each ray included in the plurality of rays to a different processing core included in a plurality of processing cores; and for each ray included in the plurality of rays, causing the processing core assigned to the ray to execute the corresponding set of importance sampling instructions on the ray to generate a direction for a secondary ray that is produced when the ray intersects a surface of an object within the

Abstract: One embodiment of a computer-implemented method for processing ray tracing operations in parallel includes receiving a plurality of rays and a corresponding set of importance sampling instructions for each ray included in the plurality of rays for processing, wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment, and each corresponding set of importance sampling instruction is based at least in part on one or more material properties associated with at least one surface of at least one object included in the 3D environment; assigning each ray included in the plurality of rays to a different processing core included in a plurality of processing cores; and for each ray included in the plurality of rays, causing the processing core assigned to the ray to execute the corresponding set of importance sampling instructions on the ray to generate a direction for a secondary ray that is produced when the ray intersects a surface of an object within the

Abstract: One embodiment of a computer-implemented method for processing ray tracing operations in parallel includes receiving a plurality of rays and a corresponding set of material shading instructions for each ray included in the plurality of rays for processing, wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment, and each corresponding set of material shading instructions is based at least in part on one or more material properties associated with at least one surface of at least one object included in the 3D environment; assigning each ray included in the plurality of rays to a different processing core included in a plurality of processing cores; and for each ray included in the plurality of rays, causing the processing core assigned to the ray to execute the corresponding set of material shading instructions on the ray to generate a color.

Abstract: One embodiment of a computer-implemented method for processing data within a fixed-function pipeline included in an execution unit includes receiving a first input from a first processing unit, wherein the first input corresponds to a first fixed-function; executing the first fixed-function on the first input to generate a first output, wherein the first fixed-function is executed on the first input prior to executing the first fixed-function on one or more inputs received from a plurality of processing cores that are processing a plurality of rays, and wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment; and transmitting the first output to the first processing unit for further processing.

Abstract: One embodiment of a computer-implemented method for decompressing a compressed texture block includes identifying a first texel included in a plurality of texels, wherein the plurality of texels forms at least a portion of a compressed texture block; determining a first location within the compressed texel block that corresponds to the first texel; and extracting the first texel from the first location without decompressing any of the other texels included in the plurality of texels.

Abstract: One embodiment of a computer-implemented method for compiling a material graph into a set of instructions for execution within an execution unit includes receiving a first material graph having a plurality of nodes, wherein each node included in the plurality of nodes represents a different surface property of a material; parsing the material graph to generate an expression tree that includes one or more expressions for each node included in the plurality of nodes; and generating a set of byte code instructions corresponding to the material graph based on the expression tree, wherein the byte code instructions are executable by a plurality of processing cores included within the execution unit.

Abstract: One embodiment of a computer-implemented method for processing ray tracing operations in parallel includes receiving a plurality of rays and a corresponding set of importance sampling instructions for each ray included in the plurality of rays for processing, wherein each ray represents a path from a light source to at least one point within a three-dimensional (3D) environment, and each corresponding set of importance sampling instruction is based at least in part on one or more material properties associated with at least one surface of at least one object included in the 3D environment; assigning each ray included in the plurality of rays to a different processing core included in a plurality of processing cores; and for each ray included in the plurality of rays, causing the processing core assigned to the ray to execute the corresponding set of importance sampling instructions on the ray to generate a direction for a secondary ray that is produced when the ray intersects a surface of an object within the

Abstract: A synchronous sequential latch array generated by an automated system for generating master-slave latch structures is disclosed. A master-slave latch structure includes N/2 rows of master-slave latch pairs, an N/2-to-1 multiplexer and control logic. N is equal to the number of latches that are included in the latch array.

Abstract: A multiplexer tree operable to control an output a sequence of data stored in a plurality of storage units in accordance with a non-linear address sequence that has less bit transition counts than a linear address sequence. The non-linear address sequence is provided to the selection inputs of the multiplexer tree and causes the levels having greater numbers of multiplexers to toggle less frequently than the levels having smaller numbers of multiplexers. The non-linear address sequence may comprise a Gray code sequence where every two adjacent addresses differ by a single bit. The non-linear address sequence may be optimized to minimize transistor switching in the multiplexer tree.

Abstract: Synthesizable code representing first-in-first out (FIFO) memories may be used to produce FIFO memories in a hardware element or system. To more efficiently use a memory element that stores the data in a FIFO, a code generator may generate a wrapper that enables the FIFO to use a memory element with different dimension (i.e., depth and width) than the FIFO's dimensions. For example, the wrapper enables a 128 deep, 1 bit wide FIFO to store data in a memory element with 16 rows that store 8 bits each. To any system communicating with the FIFO, the FIFO behaves like a 128×1 FIFO even though the FIFO is implemented using a 16×8 memory element. To do so, the code generator may generate a wrapper which enables the folded memory element to behave like a memory element that was not folded.

Abstract: One embodiment sets forth a technique for deterministic synchronization of signals that are transmitted between different clock domains. The relative phase difference between a source clock domain and a destination clock domain is characterized and the source clock and/or the destination clock are delayed as needed to generate phase-shifted versions of the source and destination clocks for use during a deterministic operating mode. The phase-shifted versions of the source and destination clocks are non-overlapping, meaning that the rising edge of the destination clock does not occur when the source clock is asserted. The non-overlapping source and destination clocks are used by a deterministic synchronization unit to ensure that signals being transmitting from the source clock domain to the destination clock domain are not sampled within a metastability window.

Abstract: Sequential write operations to a unit of compressed memory, known as a compression tile, are examined to see if the same compression tile is being written. If the same compression tile is being written, the sequential write operations are coalesced into a single write operation and the entire compression tile is overwritten with the new data. Coalescing multiple write operations into a single write operation improves performance, because it avoids the read-modify-write operations that would otherwise be needed.

Abstract: A head mounted integrated interface (HMII) is presented that may include a wearable head-mounted display unit supporting two compact high resolution screens for outputting a right eye and left eye image in support of the stereoscopic viewing, wireless communication circuits, three-dimensional positioning and motion sensors, and a processing system which is capable of independent software processing and/or processing streamed output from a remote server. The HMII may also include a graphics processing unit capable of also functioning as a general parallel processing system and cameras positioned to track hand gestures. The HMII may function as an independent computing system or as an interface to remote computer systems, external GPU clusters, or subscription computational services, The HMII is also capable linking and streaming to a remote display such as a large screen monitor.

Abstract: One embodiment of the invention sets forth a method for transmitting display data to a display device. The method includes the steps of receiving a contract for a frame of display data, preparing the frame of display data to ensure the timing requirements of the display device can be satisfied based on the contract, and transmitting the frame of display data to the display device while the contract is pending.

Abstract: Sequential write operations to a unit of compressed memory, known as a compression tile, are examined to see if the same compression tile is being written. If the same compression tile is being written, the sequential write operations are coalesced into a single write operation and the entire compression tile is overwritten with the new data. Coalescing multiple write operations into a single write operation improves performance, because it avoids the read-modify-write operations that would otherwise be needed.

Abstract: A First-in First-out (FIFO) memory comprising a latch array and a RAM array and operable to buffer data for multiple threads. Each array is partitioned into multiple sections, and each array comprises a section designated to buffer data for a respective thread. A respective latch array section is assigned higher priority to receive data for a respective thread than the corresponding RAM array section. Incoming data for the respective thread are pushed into the corresponding latch array section while it has vacancies. Upon the latch array section becoming empty, incoming data are pushed into the corresponding RAM array section during a spill-over period. The RAM array section may comprise two spill regions with only one active to receive data at a spill-over period. The allocation of data among the latch array and the spill regions of the RAM array can be transparent to external logic.