Patents by Inventor Robert A. Alfieri

Robert A. Alfieri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030212735
    Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
    Type: Application
    Filed: May 13, 2002
    Publication date: November 13, 2003
    Applicant: Nvidia Corporation
    Inventors: Gary D. Hicok, Robert A. Alfieri
  • Publication number: 20030212868
    Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. In one embodiment, functions previously performed by a complex disk controller are now integrated into a storage processing unit (SPU) that can also be deployed on the same chipset, where the SPU serves as an overall file and disk management processor.
    Type: Application
    Filed: May 13, 2002
    Publication date: November 13, 2003
    Applicant: Nvidia Corporation
    Inventors: Robert A. Alfieri, Radoslav Danilak
  • Publication number: 20030212683
    Abstract: A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. In one embodiment, file handling functions are now integrated into a storage processing unit (SPU) that can also be deployed on the same chipset, where the SPU serves as an overall file and disk management processor.
    Type: Application
    Filed: May 13, 2002
    Publication date: November 13, 2003
    Applicant: Nvidia Corporation
    Inventors: Robert A. Alfieri, Radoslav Danilak
  • Patent number: 6105053
    Abstract: An operating system for a non-uniform memory access (NUMA) multiprocessor system that utilizes a software abstraction of the NUMA system hardware representing a hierarchical tree structure to maintain the most efficient level of affinity and to maintain balanced processor and memory loads. The hierarchical tree structure includes leaf nodes representing the job processors, a root node representing at least one system resource shared by all the job processors, and a plurality of intermediate level nodes representing resources shared by different combinations of the job processors. The operating system includes a medium term scheduler for monitoring the progress of active thread groups distributed throughout the system and for assisting languishing thread groups, and a plurality of dispatchers each associated with one of the job processors for monitoring the status of the associated job processor and for obtaining thread groups for the associated job processor to execute.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: August 15, 2000
    Assignee: EMC Corporation
    Inventors: Jeffrey S. Kimmel, Robert A. Alfieri, Miles A. de Forest, William K. McGrath, Michael J. McLeod, Mark A. O'Connell, Guy A. Simpson
  • Patent number: 5745778
    Abstract: Closely related processing threads within a process in a multiprocessor system are collected into thread groups which are globally scheduled as a group based on the thread group structure's priority and scheduling parameters. The thread group structure maintains collective timeslice and CPU accounting for all threads in the group. Within each thread group, each individual thread has a local scheduling priority for scheduling among the threads in its group. The system utilizes a hierarchy of processing levels and run queues to facilitate affining thread groups with processors or groups of processors when possible. The system will tend to balance out the workload among system processors and will migrate threads groups up and down through processing levels to increase cache hits and overall performance. The system is periodically reset to avoid long term unbalanced operation conditions.
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: April 28, 1998
    Assignee: Data General Corporation
    Inventor: Robert A. Alfieri
  • Patent number: 5666486
    Abstract: A shared-disk cluster system includes a cluster membership manager framework which coordinates the joining or leaving among all nodes in a cluster including taking the multiple layers of involved subsystems through transitions. Subsystems are notified of transitions in particular order depending upon the transition, and all nodes' subsystems receiving a notification must process that notification prior to another layer of subsystems being notified. One of the subsystems registered for notification is an event manager in user space. The event manager carries out transfers of client services, including user applications, resulting from nodes joining and leaving the cluster. This includes a registration and launch service which registers a node, or multiple nodes, in a cluster which claims, or is assigned, responsibility for the service and provides an optional launching function which initiates the client service upon successful registration.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: September 9, 1997
    Assignee: Data General Corporation
    Inventors: Robert A. Alfieri, James T. Compton, Andrew R. Huber, Paul T. McGrath, Khaled S. Soufi, Brian J. Thorstad, Eric R. Vook