Patents by Inventor Robert A. Allan

Robert A. Allan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11085961
    Abstract: An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 10, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Allan Neidorff, Henry Litzmann Edwards
  • Publication number: 20210237021
    Abstract: Stable polyurea microcapsule compositions suitable for encapsulating aldehydes with a low viscosity. Also disclosed are consumer products containing such a composition and its preparation methods.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 5, 2021
    Applicant: INTERNATIONAL FLAVORS & FRAGRANCES INC.
    Inventors: Niels AKEROYD, Laura FRENCH, Robert Allan HUNTER, Yabin LEI, Lewis Michael POPPLEWELL, Volkert DE VILLENEUVE, Clementine MARTEAU-ROUSSY
  • Patent number: 11063612
    Abstract: An encoder encodes input data utilizing a binary symmetry-invariant product code including D data bits and P parity bits in each dimension. The encoder includes a half-size data array including K subarrays each having multiple rows of storage for H bits of data, where D is an integer equal to 2×H+1 and K is an integer that is 2 or greater. The encoder is configured to access K rows of data by reading a respective H-bit data word of input data from each of the multiple subarrays and K H-bit data words of duplicate data from across multiple different rows of the subarrays. The encoder further includes at least one register configured to receive the bits read from the half-size data array code and rotate them as needed, at least one row parity generator, and a column parity generator that generates column parities based on row parity.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert Allan Cyprus, Charles Camp
  • Publication number: 20210200777
    Abstract: The disclosure described herein is directed to a computerized system and method of grading and authenticating collectibles utilizing digital imaging devices and processes to provide an objective, standardized, consistent high-resolution grading of collectible objects, such as but not limited to sport and non-sport trading cards. The disclosure eliminates the subjectivity present in the human grading process and overcomes the inherent limitations of the human eye.
    Type: Application
    Filed: March 5, 2021
    Publication date: July 1, 2021
    Inventors: Stephen Brent Kass, Edward Korbel, Daniel R. Barbakow, Robert Allan Cook, Scot Maxwell, Kate Aplin, Hayden Blauzvern, Megan Shao, Ben Teng, Avi Thaker
  • Patent number: 11027289
    Abstract: The present invention relates to the use of corrosion, temperature and spark resistant electrically conductive components in wet electrostatic precipitator systems (WESPs). In particular, the present invention is directed to using a conductive composite material in the fabrication of wet electrostatic precipitator system components.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: June 8, 2021
    Assignee: Durr Systems Inc.
    Inventors: Robert A. Allan, Paul McGrath
  • Patent number: 11031754
    Abstract: Motor control centers have units or buckets with one or more sliding shutters that controllably block access to a stab isolation port based on position of the operator disconnect handle using attached cams that slide the shutter right and left. A front panel of the unit or bucket may also be configured to pivot out about a long axis associated with a bottom long side thereof.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: June 8, 2021
    Assignee: Eaton Intelligent Power Limited
    Inventors: Stephen William Oneufer, Robert Allan Morris, Daniel Boyd Kroushl
  • Patent number: 11018582
    Abstract: A circuit includes a first transistor and a second transistor coupled to the first transistor at a switch node and to a ground node. An estimator circuit receives a first signal to control an on and off state of the first transistor. The estimator circuit generates a second signal to control the on and off state of the second transistor. The second signal has a pulse width based on a pulse width of the first signal. A clocked comparator includes a clock input, a first input, and a second input. The first input receives a voltage indicative of a voltage of the switch node. The second input is coupled to a ground node. The clock input receives a third signal indicative of the second signal. The clocked comparator generates a comparator output signal. The estimator circuit adjusts the pulse width of the second signal based on the comparator output signal.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 25, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Saurav Bandyopadhyay, Michael G. Amaro, Michael Thomas DiRenzo, Thomas Matthew LaBella, Robert Allan Neidorff
  • Publication number: 20210050782
    Abstract: A switch-mode power supply circuit includes a low-side switching transistor, a high-side switching transistor, a low-side current sensing circuit, and a gate driver circuit. The low-side current sensing circuit is coupled to the low-side switching transistor and is configured to sense a current flowing through the low-side switching transistor. The gate driver circuit is coupled to the low-side current sensing circuit and the high-side switching transistor. The gate driver circuit is configured to generate a signal having a first drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being less than a threshold current, and to generate a signal having a second drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being greater than the threshold current. The first drive strength is greater than the second drive strength.
    Type: Application
    Filed: April 28, 2020
    Publication date: February 18, 2021
    Inventors: Saurav Bandyopadhyay, Thomas Matthew LaBella, Huy Le Nhat Nguyen, Michael G. Amaro, Robert Allan Neidorff
  • Publication number: 20210013805
    Abstract: In some examples, a system includes a voltage source terminal, a voltage reference terminal, a field effect transistor (FET), a current source, a comparator, and adjustment circuitry. The FET has a gate terminal and a non-gate terminal, the gate terminal coupled to the voltage source terminal. The current source is coupled to the non-gate terminal. The comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the non-gate terminal, and the second comparator input coupled to the voltage reference terminal. The adjustment circuitry has a circuitry input and a circuitry output, the circuitry input coupled to the comparator output, and the adjustment circuitry configured to adjust the circuitry output responsive to the circuitry input, in which the adjustment reduces a drive strength of the circuit.
    Type: Application
    Filed: July 13, 2020
    Publication date: January 14, 2021
    Inventors: Robert Allan NEIDORFF, Saurav BANDYOPADHYAY, Ramanathan RAMANI
  • Publication number: 20210005327
    Abstract: The present disclosure relates to personalized health, specifically molecular based health management and digital consultation. In particular, the present disclosure is directed to methods and systems for assessing the health status of an individual based on correlations between multi-omics measures (e.g., genomics, metabolomics, exposomics and proteomics) and diseases or health risks as disclosed in published research data. The disclosure also relates to methods and systems for customized counseling to individuals regarding health status and actionable measures to improve their health status.
    Type: Application
    Filed: July 3, 2020
    Publication date: January 7, 2021
    Inventors: Mohammad Ashraful Anwar, Ana Gabriela Marcu, Nitya Bourdel, Robert Allan Fraser
  • Patent number: 10840797
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first comparator, a second comparator, and a logic circuit. The first comparator includes a first input terminal coupled to a first node, a second input terminal coupled to a second node, and an output terminal. The second comparator includes a first input terminal coupled to the first node, a second input terminal coupled to a third node, and an output terminal. The logic circuit includes a first input terminal coupled to the output terminal of the first comparator, a second input terminal coupled to the output terminal of the second comparator, and an output terminal. The logic circuit is configured to determine a change in current over time based on analyzing an output signal of the first comparator and an output signal of the second comparator over a plurality of sequential cycles of operation.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Saurav Bandyopadhyay, Thomas Matthew LaBella, Robert Allan Neidorff
  • Patent number: 10831946
    Abstract: A multi-configuration massive model system. The system comprises a processor unit and a comparator configured to run on the processor unit, a memory, and a configuration manager. The comparator compares sets of parts for two or more configurations of a vehicle to form a list comprising a group of common parts and a group of unique parts. The memory is configured to store a massive model dataset of the configurations of the vehicle with a list of the group of common parts and the group of unique parts for the configurations of the vehicle. The configuration manager, configured to run on the processor unit, receives input of a selected configuration and performs an action relating to the vehicle using the massive model dataset for the selected configuration of the vehicle with the list of the group of common parts and the groups of unique parts stored in the memory.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: November 10, 2020
    Assignee: The Boeing Company
    Inventors: James J. Troy, Michael Patrick Sciarra, Nikoli E. Prazak, Steven E. Malarkey, Vladimir Karakusevic, Robert Allan Brandt, James E. Fadenrecht
  • Patent number: 10826538
    Abstract: A decoder for decoding a binary symmetry-invariant product code includes a data array having orthogonal first and second dimensions. The data array is configured to access a binary symmetry-invariant product code buffered therein along only the first dimension. The decoder also includes an error storage array for storing error locations and a first correction circuit configured to detect and correct errors in data accessed from the data array along the first dimension and to store error locations along the second dimension in the error storage array. The first correction circuit determines the error locations based on data symmetry of the symmetry-invariant product code. The decoder also includes a second correction circuit that, prior to receipt by the first correction circuit of data accessed from the data array along the first dimension, corrects the data accessed from the data array based on the error locations stored in the error storage array.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: November 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles Camp, Milos Stanisavljevic, Robert Allan Cyprus
  • Publication number: 20200303908
    Abstract: Motor control centers have units or buckets with one or more sliding shutters that controllably block access to a stab isolation port based on position of the operator disconnect handle using attached cams that slide the shutter right and left. A front panel of the unit or bucket may also be configured to pivot out about a long axis associated with a bottom long side thereof.
    Type: Application
    Filed: April 9, 2020
    Publication date: September 24, 2020
    Inventors: Stephen William Oneufer, Robert Allan Morris, Daniel Boyd Kroushl
  • Patent number: 10772510
    Abstract: The present invention pertains to devices and methods for increasing the ease of data gathering and efficiency of information flow in a clinical setting. The devices of the present invention comprise medical examination tables, dental examination chairs and vital signs monitors, all of which further comprise integrated hardware and software that allow these devices to effectively collect and communicate data in a manner that allows for greater ease of use of these devices and subsequent increased efficiency in the clinical space on the part of the clinician. The medical examination tables and dental examination chairs of the present invention preferably include at least one load sensor for measuring a subject's weight when the subject is seated thereon. The methods of the present invention are directed at using the aforementioned devices to increase ease of data collection and efficiency of care delivery within a space in which the devices are used.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: September 15, 2020
    Assignee: Midmark Corporation
    Inventors: Asad Ahmad Abu-Tarif, Robert Allan Menke, Kim M. Noone
  • Publication number: 20200200815
    Abstract: An example method comprises providing a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method comprises using the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also includes using the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further comprises using the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Robert Allan NEIDORFF, Henry Litzmann EDWARDS
  • Publication number: 20200169159
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first comparator, a second comparator, and a logic circuit. The first comparator includes a first input terminal coupled to a first node, a second input terminal coupled to a second node, and an output terminal. The second comparator includes a first input terminal coupled to the first node, a second input terminal coupled to a third node, and an output terminal. The logic circuit includes a first input terminal coupled to the output terminal of the first comparator, a second input terminal coupled to the output terminal of the second comparator, and an output terminal. The logic circuit is configured to determine a change in current over time based on analyzing an output signal of the first comparator and an output signal of the second comparator over a plurality of sequential cycles of operation.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 28, 2020
    Inventors: Saurav BANDYOPADHYAY, Thomas Matthew LaBELLA, Robert Allan NEIDORFF
  • Patent number: 10639550
    Abstract: A method of allocating computer resources in a computer system including a multicore processor having a plurality of cores. The method includes monitoring usage of the computer resources by processes executing on the computer system and determining, based upon the monitoring, that one of the processes is a high-utilization process consuming greater than a predefined threshold of the computer resources and corresponds to an application in an interactive state. One or more of the plurality of cores are allocated to the high-utilization process and other of the plurality of cores are allocated to remaining processes, thereby improving performance of the high-utilization process. Upon detecting the application has transitioned from the interactive state, one or more of the cores are previously allocated to the high-utilization process are enabled to be allocated to other than the high-utilization process.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: May 5, 2020
    Assignee: BullGuard Ltd
    Inventors: Danut Emil Argintaru, Robert Allan Clyde
  • Publication number: 20200136508
    Abstract: A circuit includes a first transistor and a second transistor coupled to the first transistor at a switch node and to a ground node. An estimator circuit receives a first signal to control an on and off state of the first transistor. The estimator circuit generates a second signal to control the on and off state of the second transistor. The second signal has a pulse width based on a pulse width of the first signal. A clocked comparator includes a clock input, a first input, and a second input. The first input receives a voltage indicative of a voltage of the switch node. The second input is coupled to a ground node. The clock input receives a third signal indicative of the second signal. The clocked comparator generates a comparator output signal. The estimator circuit adjusts the pulse width of the second signal based on the comparator output signal.
    Type: Application
    Filed: April 30, 2019
    Publication date: April 30, 2020
    Inventors: Saurav Bandyopadhyay, Michael G. Amaro, Michael Thomas DiRenzo, Thomas Matthew LaBella, Robert Allan Neidorff
  • Patent number: D900043
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 27, 2020
    Assignee: Eaton Intelligent Power Limited
    Inventors: Stephen William Oneufer, Edgar Yee, Robert Allan Morris, Daniel Boyd Kroushl