Patents by Inventor Robert A. Hutchins
Robert A. Hutchins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11381258Abstract: In one embodiment, a system includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to cause the processor to write, by the processor, data to a storage medium of a data storage system using a partial reverse concatenated modulation code. The partial reverse concatenated modulation code comprises encoding the data by applying a C2 encoding scheme prior to encoding the data by applying one or more modulation encoding schemes, followed by encoding the data by applying a C1 encoding scheme subsequent to the encoding of the data with the one or more modulation encoding schemes.Type: GrantFiled: January 6, 2020Date of Patent: July 5, 2022Assignee: Awemane Ltd.Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
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Patent number: 10680655Abstract: In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. The embodied program instructions are readable/executable by a processor to cause the processor to write, by the processor, data to a storage medium of a data storage system using a partial reverse concatenated modulation code. The partial reverse concatenated modulation code includes encoding the data by applying a C2 encoding scheme prior to encoding the data by applying one or more modulation encoding schemes, followed by encoding the data by applying a C1 encoding scheme subsequent to the encoding of the data with the one or more modulation encoding schemes. Other computer program products for writing data to a storage medium of a data storage system using a partial reverse concatenated modulation code are presented according to more embodiments.Type: GrantFiled: October 22, 2015Date of Patent: June 9, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
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Publication number: 20200153460Abstract: In one embodiment, a system includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to cause the processor to write, by the processor, data to a storage medium of a data storage system using a partial reverse concatenated modulation code. The partial reverse concatenated modulation code comprises encoding the data by applying a C2 encoding scheme prior to encoding the data by applying one or more modulation encoding schemes, followed by encoding the data by applying a C1 encoding scheme subsequent to the encoding of the data with the one or more modulation encoding schemes.Type: ApplicationFiled: January 6, 2020Publication date: May 14, 2020Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
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Patent number: 10529373Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processing circuit to cause the processing circuit to perform a method that includes reading data from a magnetic data storage medium. The processing circuit uses a tracking threshold module to detect and track positive peak amplitudes and negative peak amplitudes of a readback waveform during the data reading. Asymmetry compensation is performed on the data based on input from the tracking threshold module. The asymmetry compensation does not rely on an input except from the tracking threshold module in order to perform the asymmetry compensation.Type: GrantFiled: May 31, 2018Date of Patent: January 7, 2020Assignee: International Business Machines CorporationInventor: Robert A. Hutchins
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Patent number: 10484018Abstract: In one embodiment, a method includes writing data to a storage medium, via a write channel, by applying a partial reverse concatenated modulation code to the data prior to storing encoded data to the storage medium. The applying the partial reverse concatenated modulation code to the data includes application of a C2 encoding scheme to the data to produce C2-encoded data prior to application of one or more modulation encoding schemes to the C2-encoded data to produce modulated data, followed by application of a C1 encoding scheme to the modulated data subsequent to the application of the one or more modulation encoding schemes to produce the encoded data.Type: GrantFiled: January 12, 2017Date of Patent: November 19, 2019Assignee: International Business Machines CorporationInventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
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Patent number: 10401632Abstract: A planar line generator including a first planar surface extending in a first direction, a second planar surface facing the first planar surface, and a beam splitter in front of the second planar surface, the beam splitter configured to output, from light incident thereon, an undeflected beam, a first beam deflected to a first side of the undeflected beam along the first direction, and a second beam deflected to a second side of the undeflected beam along the first direction, wherein the second planar surface includes a line diffuser configured to receive the undeflected beam, and first and second diffusers having a design different from the line diffuser, the first and second diffusers being configured to receive the first and second beams, respectively.Type: GrantFiled: March 9, 2015Date of Patent: September 3, 2019Assignee: FLIR SYSTEMS, INC.Inventors: Robert Hutchins, Alan D. Kathman
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Patent number: 10298272Abstract: In one embodiment, a system includes a controller and logic integrated with and/or executable by the controller. The logic is configured to perform iterative decoding on encoded data to obtain decoded data. The logic is also configured to perform post-decoding error diagnostics on a first portion of the decoded data in response to not obtaining a valid product codeword in the first portion after the iterative decoding of the encoded data. Other systems, methods, and computer program products for producing post-decoding error signatures are presented in accordance with more embodiments.Type: GrantFiled: June 13, 2016Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: Steven R. Bentley, Roy D. Cideciyan, Robert A. Hutchins, Keisuke Tanaka
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Patent number: 10152375Abstract: In one embodiment, a system includes a controller and logic integrated with and/or executable by the controller. The logic is configured to read data stored as a plurality of first codeword sets on a first write section of a magnetic medium. The logic is also configured to read at least some of the data stored as one or more rewritten codeword sets on a rewrite section of the magnetic medium. A length of at least one rewritten row stored to the rewrite section of the magnetic medium is greater than: a length of another rewritten row in the same rewritten codeword set, and/or a length of at least one row in a codeword set stored to the first write section of the magnetic medium.Type: GrantFiled: May 13, 2016Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Roy D. Cideciyan, Simeon Furrer, Robert A. Hutchins, Keisuke Tanaka
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Publication number: 20180277155Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processing circuit to cause the processing circuit to perform a method that includes reading data from a magnetic data storage medium. The processing circuit uses a tracking threshold module to detect and track positive peak amplitudes and negative peak amplitudes of a readback waveform during the data reading. Asymmetry compensation is performed on the data based on input from the tracking threshold module. The asymmetry compensation does not rely on an input except from the tracking threshold module in order to perform the asymmetry compensation.Type: ApplicationFiled: May 31, 2018Publication date: September 27, 2018Inventor: Robert A. Hutchins
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Patent number: 10055289Abstract: In one embodiment, a system includes a controller and logic integrated with and/or executable by the controller. The logic is configured to cause data to be written to a first write section of a magnetic medium as a plurality of first codeword sets, and cause at least some of the data to be written to a rewrite section of the magnetic medium as one or more rewritten codeword sets. A length of at least one rewritten row stored to the rewrite section of the magnetic medium is greater than either a length of another rewritten row in the same rewritten codeword set and/or a length of at least one row in a codeword set stored to the first write section of the magnetic medium.Type: GrantFiled: May 13, 2016Date of Patent: August 21, 2018Assignee: International Business Machines CorporationInventors: Roy D. Cideciyan, Simeon Furrer, Robert A. Hutchins, Keisuke Tanaka
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Patent number: 10020021Abstract: In one embodiment, a system includes one or more processors and logic integrated with and/or executable by the one or more processors. The logic is configured to cause at least one of the processors to detect positive peak amplitudes and negative peak amplitudes of an unequalized readback signal that exhibits imperfect or bi-modal waveform peaks using a peak tracking threshold module positioned at an input to an equalizer. Also, the logic is configured to cause the at least one of the processors to track the positive peak amplitudes and the negative peak amplitudes of the unequalized readback signal in a record. Moreover, the logic is configured to cause the at least one of the processors to provide, as an input to an asymmetry compensator, the record of the peak amplitudes and the negative peak amplitudes determined from the unequalized readback signal.Type: GrantFiled: July 21, 2017Date of Patent: July 10, 2018Assignee: International Business Machines CorporationInventor: Robert A. Hutchins
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Patent number: 9985658Abstract: In one embodiment, a method includes receiving data and in an iterative process until decoded data is output or a predetermined number of full iterations have occurred: C1 decoding all first subsets of the data, determining whether to stop decoding the data after the C1 decoding, incrementing a half iteration counter to indicate completion of a half iteration, C2 decoding all second subsets of the data two or more times in each half iteration using two or more C2-decoding methods in response to a determination that a second subset is not decoded successfully using a first C2-decoding method, determining whether to stop decoding the data after the C2 decoding, incrementing the half iteration counter to indicate completion of another half iteration, and outputting the set of decoded data in response to a determination that all subsets of the data are decoded successfully.Type: GrantFiled: May 1, 2017Date of Patent: May 29, 2018Assignee: International Business Machines CorporationInventors: Roy D. Cideciyan, Simeon Furrer, Robert A. Hutchins
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Publication number: 20170323662Abstract: In one embodiment, a system includes one or more processors and logic integrated with and/or executable by the one or more processors. The logic is configured to cause at least one of the processors to detect positive peak amplitudes and negative peak amplitudes of an unequalized readback signal that exhibits imperfect or bi-modal waveform peaks using a peak tracking threshold module positioned at an input to an equalizer. Also, the logic is configured to cause the at least one of the processors to track the positive peak amplitudes and the negative peak amplitudes of the unequalized readback signal in a record. Moreover, the logic is configured to cause the at least one of the processors to provide, as an input to an asymmetry compensator, the record of the peak amplitudes and the negative peak amplitudes determined from the unequalized readback signal.Type: ApplicationFiled: July 21, 2017Publication date: November 9, 2017Inventor: Robert A. Hutchins
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Patent number: 9799370Abstract: In one general embodiment, a method includes determining a sampling interval for an interpolator using at least one parameter. The method further includes applying the sampling interval to the interpolator in response to determining the sampling interval. In another general embodiment, an apparatus includes an interpolator and a controller. The controller is configured to determine a sampling interval for the interpolator using at least one parameter. The controller is also configured to apply the sampling interval to the interpolator in response to determining the sampling interval.Type: GrantFiled: January 5, 2017Date of Patent: October 24, 2017Assignee: International Business Machines CorporationInventors: Giovanni Cherubini, Simeon Furrer, Robert A. Hutchins, Jens Jelitto
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Patent number: 9767842Abstract: In one embodiment, a system for processing data includes a processor and logic integrated with and/or executable by the processor. The logic is configured to detect and track positive peak amplitudes and negative peak amplitudes of a readback waveform during data reading using a tracking threshold module, and to detect and track positive peak amplitudes and negative peak amplitudes of the readback waveform during the data reading at an input to an equalizer using a second tracking threshold module in response to reading a data set separator (DSS). Moreover, the logic is configured to perform asymmetry compensation on the data using an asymmetry compensator in an asymmetry compensation loop based on input from the tracking threshold module when not reading a DSS and based on input from the second tracking threshold module when reading a DSS, an output of the asymmetry compensator being provided to the equalizer.Type: GrantFiled: September 8, 2015Date of Patent: September 19, 2017Assignee: International Business Machines CorporationInventor: Robert A. Hutchins
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Patent number: 9761267Abstract: According to one embodiment, a system for processing data includes a processor and logic integrated with and/or executable by the processor. The logic is configured to individually set, for each of one or more range-constrained finite impulse response (FIR) filter taps configured for use in a FIR filter, a predetermined range of values suitable for controlling an equalizer response. The logic is also configured to pass data through the equalizer comprising the FIR filter to obtain equalized data. Each of the one or more range-constrained FIR filter taps are individually adaptive within its predetermined range of values. Also, the data is read from a magnetic storage medium.Type: GrantFiled: March 31, 2016Date of Patent: September 12, 2017Assignee: International Business Machines CorporationInventor: Robert A. Hutchins
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Publication number: 20170237447Abstract: In one embodiment, a method includes receiving data and in an iterative process until decoded data is output or a predetermined number of full iterations have occurred: C1 decoding all first subsets of the data, determining whether to stop decoding the data after the C1 decoding, incrementing a half iteration counter to indicate completion of a half iteration, C2 decoding all second subsets of the data two or more times in each half iteration using two or more C2-decoding methods in response to a determination that a second subset is not decoded successfully using a first C2-decoding method, determining whether to stop decoding the data after the C2 decoding, incrementing the half iteration counter to indicate completion of another half iteration, and outputting the set of decoded data in response to a determination that all subsets of the data are decoded successfully.Type: ApplicationFiled: May 1, 2017Publication date: August 17, 2017Inventors: Roy D. Cideciyan, Simeon Furrer, Robert A. Hutchins
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Patent number: 9712188Abstract: In one embodiment, a method includes reading packets of data from M parallel data tracks of a magnetic tape to obtain a plurality of (D+P)-symbol codewords which are logically arranged in nM encoded blocks, each packet including a row of an encoded block, where each encoded block includes an array having rows and columns of code symbols, wherein symbols of each of the (D+P)-symbol codewords are distributed over corresponding rows of the nM encoded blocks, decoding sub-blocks from rows and columns of a plurality of product codewords from the nM encoded blocks, each product codeword including a logical array of code symbols having the rows which include respective row codewords and the columns which include respective column codewords, where each sub-block includes a logical array having rows and columns of data symbols, combining the sub-blocks to form a block of data, and outputting the block of data.Type: GrantFiled: May 4, 2015Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Roy D. Cideciyan, Simeon Furrer, Robert A. Hutchins, Mark A. Lantz
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Publication number: 20170170849Abstract: In one embodiment, a system includes a controller and logic integrated with and/or executable by the controller. The logic is configured to perform iterative decoding on encoded data to obtain decoded data. The logic is also configured to perform post-decoding error diagnostics on a first portion of the decoded data in response to not obtaining a valid product codeword in the first portion after the iterative decoding of the encoded data. Other systems, methods, and computer program products for producing post-decoding error signatures are presented in accordance with more embodiments.Type: ApplicationFiled: June 13, 2016Publication date: June 15, 2017Inventors: Steven R. Bentley, Roy D. Cideciyan, Robert A. Hutchins, Keisuke Tanaka
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Patent number: 9673839Abstract: In one embodiment, a method for decoding data includes iteratively C1 decoding all first subsets of a set of data two or more times in each half iteration using two or more C1-decoding methods when a first subset is not decoded successfully using a first C1 decoding, determining whether to stop decoding the set of data after the C1 decoding and output results of the C1 decoding, incrementing a half iteration counter to indicate completion of a half iteration in response to decoding not being stopped, C2 decoding all second subsets of the set of data, determining whether to stop decoding the set of data after the C2 decoding and output results of the C2 decoding, incrementing the half iteration counter to indicate completion of another half iteration in response to decoding not being stopped, and outputting decoded data when all subsets of the set of data are decoded successfully.Type: GrantFiled: February 1, 2016Date of Patent: June 6, 2017Assignee: International Business Machines CorporationInventors: Roy D. Cideciyan, Simeon Furrer, Robert A. Hutchins