Patents by Inventor Robert A. May

Robert A. May has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260165160
    Abstract: Recesses formed at the tops and bottoms of through glass via (TGV) metal regions during TGV formation can create glass-metal-air triple points. These triple points can be the source of cracks or other damage to a glass layer during thermal treatment in downstream processing due to the coefficient of thermal expansion mismatch between the TGV metal and the glass. To relieve stress at the triple points, the recesses can be filled with a conductive paste or a metal layer formed via electroless plating. Alternatively, during TGV formation, regions of low-modulus dielectric material can be formed where the triple points would otherwise be formed. The low-modulus dielectric material can provide local stress relief and mitigate the formation of glass layer damage in downstream processing.
    Type: Application
    Filed: December 10, 2024
    Publication date: June 11, 2026
    Inventors: Hiroki Tanaka, Nanqi Bao, Haobo Chen, Brandon Christian Marin, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Bohan Shan, Robert A. May, Jacob Vehonsky
  • Publication number: 20260164539
    Abstract: Recesses formed at the tops and bottoms of through glass via (TGV) metal regions during TGV formation can create glass-metal-air triple points. These triple points can be the source of cracks or other damage to a glass layer during thermal treatment in downstream processing due to the coefficient of thermal expansion mismatch between the TGV metal and the glass. To relieve stress at the triple points, the recesses can be filled with a conductive paste or a metal layer formed via electroless plating. Alternatively, during TGV formation, regions of low-modulus dielectric material can be formed where the triple points would otherwise be formed. The low-modulus dielectric material can provide local stress relief and mitigate the formation of glass layer damage in downstream processing.
    Type: Application
    Filed: December 10, 2024
    Publication date: June 11, 2026
    Applicant: Intel Corporation
    Inventors: Hiroki Tanaka, Haobo Chen, Xiao Liu, Brandon Christian Marin, Kyle McElhinny, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Bohan Shan, Robert A. May, Jacob Vehonsky
  • Patent number: 12652315
    Abstract: Systems and methods for remote monitoring of a Security Operations Center (SOC) via a mobile application are provided. According to one embodiment, a management service retrieves information regarding multiple network elements that are associated with an enterprise network and extracts parameters of the monitored network elements from the retrieved information. The management service prioritizes the monitored network elements by determining a severity level associated with security-related issues of the network elements and generates various monitoring views that summarize in real time various categories of potential security-related issues detected by the SOC. Further, the management service assigns a priority to each monitoring view and displays a video on the display device that cycles through monitoring views in accordance with their respective assigned priorities.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: June 9, 2026
    Assignee: FORTINET, INC.
    Inventors: Robert A. May, Jordan E. Thompson
  • Publication number: 20260090432
    Abstract: An apparatus comprising a package substrate, the package substrate comprising a glass structure; at least one buildup layer above the glass structure; and at least one buildup layer below the glass structure; wherein the glass structure comprises a first portion having a first thickness and a second portion that extends outward from the first portion, wherein the second portion has a second thickness that is smaller than the first thickness.
    Type: Application
    Filed: September 26, 2024
    Publication date: March 26, 2026
    Inventors: Jeremy D. Ecton, Brandon Christian Marin, Hanyu Song, Hiroki Tanaka, Whitney M. Bryks, Haobo Chen, Gang Duan, Benjamin T. Duong, Yonggang Li, Robert A. May, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Bohan Shan, Jacob Vehonsky, Fanyi Zhu
  • Patent number: 12574288
    Abstract: Various embodiments provide systems and methods for automating an SD-WAN setup process.
    Type: Grant
    Filed: June 21, 2024
    Date of Patent: March 10, 2026
    Assignee: Fortinet, Inc.
    Inventor: Robert A. May
  • Patent number: 12574413
    Abstract: Systems, devices, and methods are discussed for treating a number of network security devices in a cooperative security fabric as a unified object for configuration purposes.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: March 10, 2026
    Assignee: Fortinet, Inc.
    Inventors: Michael Xie, Robert A. May, Lino Xu, Jordan E. Thompson
  • Publication number: 20260005114
    Abstract: Architectures and process flows for frames for glass core hybrid panels for semiconductor packaging. The glass core includes a layer of glass defined by a planar area enclosed by one or more edges that are substantially orthogonal to the planar area and at least one through-glass via (TGV) in the layer of glass, substantially filled with a conductive material. The frame comprises a coefficient of thermal expansion (CTE) that can be manipulated based on selection of frame material and/or percentage of copper in the frame material. The frame has a CTE of less than 11. The frame can enclose a panel, sub-panel or wafer and can include one or more cavities therein for respective glass cores.
    Type: Application
    Filed: June 27, 2024
    Publication date: January 1, 2026
    Applicant: Intel Corporation
    Inventors: Benjamin T. Duong, Pratyush Mishra, Robert A. May, Soham Agarwal, Kristof Darmawikarta, Gang Duan, Jeremy D. Ecton, Jung Kyu Han, Thomas S. Heaton, Kari E. Hernandez, Tarek A. Ibrahim, Andrew Matthew Jimenez, Brandon Christian Marin, Lilia May, Pratyasha Mohapatra, Son Van Nguyen, Srinivas Venkata Ramanuja Pietambaram, Bohan Shan, Hiroki Tanaka, David Vickery, Yekan Wang, Zhixin Xie
  • Publication number: 20260005115
    Abstract: An apparatus comprising a package substrate, the package substrate comprising a glass layer, a first layer comprising a photo-imageable dielectric (PID) material above the glass layer, a second layer below the glass layer, the second layer comprising the PID material, at least one buildup layer above the first layer, and at least one buildup layer below the second layer.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 1, 2026
    Applicant: Intel Corporation
    Inventors: Andrew Matthew Jimenez, Manohar Konchady, Mahdi Mohammadighaleni, Hiroki Tanaka, Ehsan Zamani, Whitney M. Bryks, Haobo Chen, Gang Duan, Benjamin T. Duong, Darko Grujicic, Jung Kyu Han, Thomas S. Heaton, Shayan Kaviani, Brandon Christian Marin, Robert A. May, Seyyed Yahya Mousavi, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Bohan Shan, Joshua J. Stacey, Elham Tavakoli, Yekan Wang, Zhixin Xie
  • Patent number: 12476937
    Abstract: Systems, devices, and methods are discussed for treating a number of network security devices in a cooperative security fabric using a cloud based root.
    Type: Grant
    Filed: July 4, 2022
    Date of Patent: November 18, 2025
    Assignee: Fortinet, Inc.
    Inventor: Robert A. May
  • Patent number: 12432123
    Abstract: Systems, devices, and methods are discussed for automating incident management.
    Type: Grant
    Filed: June 26, 2024
    Date of Patent: September 30, 2025
    Assignee: Fortinet, Inc.
    Inventor: Robert A. May
  • Publication number: 20250218915
    Abstract: An apparatus comprising a package substrate comprising a core layer; a pedestal embedded in the core layer; and a structure comprising a passive circuit component, wherein the structure is above the pedestal and is embedded in the core layer.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Tolga Acikalin, Soham Agarwal, Benjamin T. Duong, Jeremy D. Ecton, Kari E. Hernandez, Brandon Christian Marin, Pratyush Mishra, Pratyasha Mohapatra, Srinivas V. Pietambaram, Marcel M. Said, Gang Duan, Hiroki Tanaka, Robert A. May, Bai Nie, Sanjay Tharmarajah, Bohan Shan
  • Publication number: 20250125275
    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Aleksandar ALEKSOV, Adel A. ELSHERBINI, Kristof DARMAWIKARTA, Robert A. MAY, Sri Ranga Sai BOYAPATI
  • Publication number: 20250125277
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Srinivas V. PIETAMBARAM, Sri Ranga Sai BOYAPATI, Robert A. MAY, Kristof DARMAWIKARTA, Javier SOTO GONZALEZ, Kwangmo LIM
  • Patent number: 12218069
    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: February 4, 2025
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert A. May, Sri Ranga Sai Boyapati
  • Patent number: 12218071
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: February 4, 2025
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta, Javier Soto Gonzalez, Kwangmo Lim
  • Publication number: 20240422171
    Abstract: Various embodiments provide systems and methods for providing security in a ZTNA system.
    Type: Application
    Filed: August 28, 2024
    Publication date: December 19, 2024
    Applicant: Fortinet, Inc.
    Inventor: Robert A. May
  • Publication number: 20240414066
    Abstract: Systems, devices, and methods are discussed for automating incident management.
    Type: Application
    Filed: June 26, 2024
    Publication date: December 12, 2024
    Applicant: Fortinet, Inc.
    Inventor: Robert A. May
  • Patent number: 12149540
    Abstract: Various embodiments provide systems and methods for providing security in a ZTNA system.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: November 19, 2024
    Assignee: Fortinet, Inc.
    Inventor: Robert A. May
  • Publication number: 20240340221
    Abstract: Various embodiments provide systems and methods for automating an SD-WAN setup process.
    Type: Application
    Filed: June 21, 2024
    Publication date: October 10, 2024
    Applicant: Fortinet, Inc.
    Inventor: Robert A. May
  • Patent number: 12101231
    Abstract: Systems, devices, and methods are discussed for automating incident management.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: September 24, 2024
    Assignee: Fortinet, Inc.
    Inventor: Robert A. May