Patents by Inventor Robert A. May

Robert A. May has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250139187
    Abstract: In some implementations, a style system may receive, from a repository, a plurality of files associated with an entity. The style system may apply a machine learning model to the plurality of files to determine a set of rules associated with images or text included in the plurality of files. The style system may generate a document that indicates the set of rules and may output, to a user device, the document.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 1, 2025
    Inventors: Leeyat Bracha TESSLER, Claire M. ROWLETT, Robert MAYS, Daniel E. MILLER, Youbing YIN
  • Publication number: 20250125277
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Srinivas V. PIETAMBARAM, Sri Ranga Sai BOYAPATI, Robert A. MAY, Kristof DARMAWIKARTA, Javier SOTO GONZALEZ, Kwangmo LIM
  • Publication number: 20250125275
    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Aleksandar ALEKSOV, Adel A. ELSHERBINI, Kristof DARMAWIKARTA, Robert A. MAY, Sri Ranga Sai BOYAPATI
  • Publication number: 20250124153
    Abstract: In some implementations, a rules system may receive a digital file associated with an entity. The rules system may receive, from a user device, an indication of a set of rules associated with the entity. The rules system may apply a model, associated with the set of rules, to determine whether the digital file is compliant with the set of rules and may determine at least one compliance result based on output from the model. The rules system may transmit, to the user device, instructions for a user interface that indicates the at least one compliance result.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 17, 2025
    Inventors: Anne Tyler SCHAFFER, Robert MAYS
  • Publication number: 20250112100
    Abstract: An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to the first package conductive features. Third interconnects excluding solder couple the bridge with the second package conductive features. The bridge couples the first and second IC die with each other, and the first and second IC die with the second package conductive features. A pitch of conductive features in the first interconnects is less than a pitch of conductive features in the second interconnects.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Robert May, Hiroki Tanaka, Tarek Ibrahim, Lilia May, Jason Gamba, Benjamin Duong, Brandon Marin, Srinivas Pietambaram, Gang Duan, Suddhasattwa Nad, Jeremy Ecton
  • Publication number: 20250112165
    Abstract: Anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. An example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Brandon Marin, Hiroki Tanaka, Robert May, Srinivas Pietambaram, Gang Duan, Suddhasattwa Nad, Numair Ahmed, Jeremy Ecton, Benjamin Taylor Duong, Bai Nie, Haobo Chen, Xiao Liu, Bohan Shan, Shruti Sharma, Mollie Stewart
  • Patent number: 12253722
    Abstract: An optical package comprising an optical die that is electrically coupled to a package substrate, and an optical interconnect adjacent the optical die. The optical interconnect comprises a first polarizing filter adjacent to a first lens, a second polarizing filter adjacent to a second lens; and a film comprising a magnetic material between the first polarizing filter and the second polarizing filter. The second polarizing filter is rotated with respect to the first polarizing filter and the magnetic material is to rotate a polarization vector of light incoming to the optical interconnect. An optical fiber interface port is immediately adjacent to the first lens. The second lens is immediately adjacent to an optical interface of the optical die.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: March 18, 2025
    Assignee: Intel Corporation
    Inventors: Hiroki Tanaka, Kristof Darmawikarta, Brandon Marin, Robert May, Sri Ranga Sai Boyapati
  • Publication number: 20250069902
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Applicant: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Patent number: 12218069
    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: February 4, 2025
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert A. May, Sri Ranga Sai Boyapati
  • Patent number: 12218576
    Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.
    Type: Grant
    Filed: March 8, 2024
    Date of Patent: February 4, 2025
    Assignee: Skyworks Solutions, Inc.
    Inventors: Michael Robert May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamas Marozsak, Andras V. Horvath
  • Patent number: 12218071
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: February 4, 2025
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta, Javier Soto Gonzalez, Kwangmo Lim
  • Publication number: 20250022786
    Abstract: Methods and apparatus for edge protected glass cores are disclosed herein. An example package substrate includes a first glass layer including a first surface, a second surface opposite the first surface, and first lateral surfaces extending between the first and second surfaces, the first glass layer having a first via extending between the first surface and the second surface; and a dielectric material in contact with the first surface of the first glass layer and in contact with the first lateral surfaces of the first glass layer.
    Type: Application
    Filed: September 27, 2024
    Publication date: January 16, 2025
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Hiroki Tanaka, Haobo Chen, Brandon Christian Marin, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Jason Gamba, Bohan Shan, Robert May, Benjamin Taylor Duong, Bai Nie, Whitney Bryks
  • Publication number: 20240424732
    Abstract: A method for preparing virtual build volumes for the manufacture of three-dimensional objects. The virtual build volume represents an actual build volume over which one or more objects are to be built. The method includes the steps of: (a) receiving one or more object models, the object model(s) defining the intended dimensions of each of the objects; (b) applying a transformation to an initial virtual build volume to create a reduced virtual build volume smaller than the virtual build volume; (c) positioning the object model(s) within the reduced virtual build volume; and (d) applying an inverse transformation to expand the reduced virtual build volume to create an expanded virtual build volume including expanded object model(s); wherein each of the expanded object model(s) is larger than the respective object model(s).
    Type: Application
    Filed: April 21, 2023
    Publication date: December 26, 2024
    Inventor: Robert May
  • Patent number: 12176223
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Publication number: 20240422171
    Abstract: Various embodiments provide systems and methods for providing security in a ZTNA system.
    Type: Application
    Filed: August 28, 2024
    Publication date: December 19, 2024
    Applicant: Fortinet, Inc.
    Inventor: Robert A. May
  • Publication number: 20240414066
    Abstract: Systems, devices, and methods are discussed for automating incident management.
    Type: Application
    Filed: June 26, 2024
    Publication date: December 12, 2024
    Applicant: Fortinet, Inc.
    Inventor: Robert A. May
  • Publication number: 20240414159
    Abstract: Systems, devices, and methods are discussed for providing virtualized ZTNA control across multiple networks.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 12, 2024
    Applicant: Fortinet, Inc.
    Inventor: Robert May
  • Patent number: 12149540
    Abstract: Various embodiments provide systems and methods for providing security in a ZTNA system.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: November 19, 2024
    Assignee: Fortinet, Inc.
    Inventor: Robert A. May
  • Patent number: 12148703
    Abstract: Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Robert Sankman, Robert May
  • Patent number: 12135069
    Abstract: The auxiliary suspension device is relatively neutral at rest and responds in coordination with the existing suspension system upon application of a load. The redundant suspension device has an inflatable bellow that is mounted between a vehicle's frame and an existing vehicle suspension element.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: November 5, 2024
    Assignee: RB Distribution, Inc.
    Inventors: Tam Van Nguyen, Matthew Robert May, Sean Cattie, Bryan McMasters, David Cimbolo