Patents by Inventor Robert A. May

Robert A. May has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11412016
    Abstract: Systems and methods for demonstrating network security products in a virtual conference and providing training to attendees of a network security training session in the virtual conference through the use of gamification are provided. A server generates a dedicated virtual environment for a particular attendee. A three-dimensional (3D) user interface for the virtual conference is presented on a display of the particular attendee, which represents a simulated conference environment with each network security product being demonstrated as a virtual booth represented in the conference environment. A game client causes the particular attendee to navigate in the 3D user interface to a first virtual booth to access a first learning objective relating to demonstration of a first network security product corresponding to the first booth. A progress report, which is maintained by the server, is used to notify regarding other learning objectives that are of potential interest to the particular attendee.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: August 9, 2022
    Assignee: Fortinet, Inc.
    Inventors: Robert A. May, Jordan E. Thompson, Jamie Pate
  • Patent number: 11393766
    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert A. May, Sri Ranga Sai Boyapati
  • Publication number: 20220223527
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 14, 2022
    Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN
  • Patent number: 11373951
    Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Jeremy D. Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Vahidreza Parichehreh, Leonel R. Arana, Chung Kwang Tan, Robert A. May
  • Publication number: 20220183157
    Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: INTEL CORPORATION
    Inventors: Kristof Darmawikarta, Robert A. May, Yikang Deng, Ji Yong Park, Maroun D. Moussallem, Amruthavalli P. Alur, Sri Ranga Sai Boyapati, Lilia May
  • Publication number: 20220181166
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Patent number: 11351202
    Abstract: The invention relates to the treatment of various injuries, disorders, dysfunctions, diseases, and the like of the brain with MAPCs, particularly in some aspects, to the treatment of the same resulting from hypoxia, including that caused by systemic hypoxia and that caused by insufficient blood supply. In some further particulars the invention relates, for example, to the treatment of hypoxic ischemic brain injury with MAPCs, in children for example, and to the treatment of cortical infarcts and stroke with MAPCs in adults, for example.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 7, 2022
    Assignees: ABT HOLDING COMPANY, AUGUSTA UNIVERSITY RESEARCH INSTITUTE, INC.
    Inventors: Robert Mays, Robert J. Deans, David C. Hess, James E. Carroll, Cesar V. Borlongan
  • Patent number: 11344684
    Abstract: A refill assembly (129) for use in a medicinal inhaler (100). The refill assembly includes a patient port (110), and an adapter (118) configured to cause a dose of medicament to be released. The adapter is movable between a first position in which a dose of medicament is not released and a second position in which a dose of medicament is released. The refill assembly further includes a lockout mechanism positioned to lock the adapter in its first position, and a lockout override actuator (223). The lockout override actuator is movable between a first position in which the lockout mechanism is in a first locked state, and a second position in which the lockout mechanism is in a second unlocked state and the adapter is movable from its first position to its second position even when the refill assembly is not coupled to a reusable assembly.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: May 31, 2022
    Assignee: Kindeva Drug Delivery L.P.
    Inventors: William T. Richardson, Robert May, Christopher B. J. Groombridge
  • Publication number: 20220152289
    Abstract: An ophthalmic irrigator-aspirator has a handpiece with aspiration and irrigation openings through its distal end. A tip component connects to the handpiece and has an aspiration cannula. A flexible sleeve has an annular hub for watertight connection to the handpiece or a base portion of the tip. The sleeve has an intermediate portion that forms a channel for an irrigation fluid along the exterior of the cannula to an irrigation port in the sleeve. The distal end portion of the sleeve is sized for a watertight connection over the distal portion of the cannula. Such distal end portion of the sleeve has an aspiration port in communication with the cannula aspiration port. The sleeve proximate, intermediate, and distal portions are integral with each other and are formed of a resilient material that allows the sleeve to be tightly fitted on the handpiece or tip base portion and the cannula.
    Type: Application
    Filed: August 23, 2021
    Publication date: May 19, 2022
    Inventors: Kenneth J. Wiljanen, Robert May, Lawrence Laks
  • Patent number: 11322444
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
  • Publication number: 20220130748
    Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 28, 2022
    Applicant: INTEL CORPORATION
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
  • Publication number: 20220118026
    Abstract: The invention relates to the treatment of various injuries, disorders, dysfunctions, diseases, and the like of the brain with MAPCs, particularly in some aspects, to the treatment of the same resulting from hypoxia, including that caused by systemic hypoxia and that caused by insufficient blood supply. In some further particulars the invention relates, for example, to the treatment of hypoxic ischemic brain injury with MPACs, in children, for example, and to the treatment of cortical infarcts and stroke with MAPCs in adults, for example.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 21, 2022
    Applicants: ABT Holding Company, AUGUSTA UNIVERSITY RESEARCH INSTITUTE, INC.
    Inventors: Robert MAYS, Robert J. DEANS, David C. HESS, James E. CARROLL, Cesar V. BORLONGAN
  • Publication number: 20220122935
    Abstract: An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Applicant: Intel Corporation
    Inventors: Kristof Darmawikarta, Sri Ranga Sai Boyapati, Hiroki Tanaka, Robert A. May
  • Patent number: 11309192
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Publication number: 20220110982
    Abstract: The invention relates to the treatment of various injuries, disorders, dysfunctions, diseases, and like of the brain with MAPCs, particularly in some aspects, to the treatment of the same resulting from hypoxia, including that caused by systemic hypoxis and that caused by insufficient blood supply. In some further particulars the invntion relates, for example, to the treatment of hypoxic ischemic brain injury with MAPCs, in children, for example, and to the treatment of cortical infants and stroke with MAPCs in adults, for example.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicants: ABT Holding Company, AUGUSTA UNIVERSITY RESEARCH INSTITUTE, INC.
    Inventors: Robert MAYS, Robert J. Deans, David C. Hess, James E. Carroll, Cesar V. Borlongan
  • Patent number: 11272619
    Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Robert A. May, Yikang Deng, Ji Yong Park, Maroun D. Moussallem, Amruthavalli P. Alur, Sri Ranga Sai Boyapati, Lilia May
  • Patent number: 11264239
    Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Hiroki Tanaka, Aleksandar Aleksov, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta
  • Patent number: 11264307
    Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Hiroki Tanaka, Robert A. May, Kristof Darmawikarta, Changhua Liu, Chung Kwang Tan, Srinivas Pietambaram, Sri Ranga Sai Boyapati
  • Patent number: 11264346
    Abstract: An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Sri Ranga Sai Boyapati, Hiroki Tanaka, Robert A. May
  • Patent number: 11254178
    Abstract: A suspension strut including an air spring unit and a damper unit that are aligned on a common axis is disclosed. The air spring unit includes a rolling tube having a flared terminal end that extends over a damper tube associated with the damper unit. The damper tube has a circumferential groove formed in an outer diameter of the damper tube. A retaining ring has a greater outer diameter than the outer diameter of the damper tube and is positioned in the circumferential groove. A base has an inner diameter less than the outer diameter of the retaining ring, and an outer diameter smaller than the predetermined diameter of the flared free end, and is supported on the retaining ring. A torsion element fits around the damper tube and within the flared free end.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 22, 2022
    Assignee: RB DISTRIBUTION, INC.
    Inventors: Tam Van Nguyen, Matthew Robert May