Patents by Inventor Robert A. Shearer

Robert A. Shearer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Instruction set architecture with opcode lookup using memory attribute
    Patent number: 9292290
    Abstract: A circuit arrangement decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Instruction set architecture with opcode lookup using memory attribute
    Patent number: 9286071
    Abstract: A method decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • General purpose processing unit with low power digital signal processing (DSP) mode
    Patent number: 9274591
    Abstract: A method and circuit arrangement utilize a general purpose processing unit having a low power DSP mode for reconfiguring the general purpose processing unit to efficiently execute DSP workloads with reduced power consumption. When in a DSP mode, one or more of a data cache, an execution unit, and simultaneous multithreading may be disabled to reduce power consumption and improve performance for DSP workloads. Furthermore, partitioning of a register file to support multithreading, and register renaming functionality, may be disabled to provide an expanded set of registers for use with DSP workloads. As a result, a general purpose processing unit may be provided with enhanced performance for DSP workloads with reduced power consumption, while also not sacrificing performance for other non-DSP/general purpose workloads.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Dynamic thread status retrieval using inter-thread communication
    Patent number: 9256574
    Abstract: A circuit arrangement, method, and program product for dynamically providing a status of a hardware thread/hardware resource independent of the operation of the hardware thread/hardware resource using an inter-thread communication protocol. A master hardware thread may be configured to communicate status requests to associated slave hardware threads and/or hardware resources. Each slave hardware thread/hardware resource may be configured with hardware logic configured to automatically determine status information for the slave hardware thread/hardware resource and communicate a status response to the master hardware thread independent of the operation of the slave hardware thread/hardware resource.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer
  • Dynamic thread status retrieval using inter-thread communication
    Patent number: 9256573
    Abstract: A circuit arrangement, method, and program product for dynamically providing a status of a hardware thread/hardware resource independent of the operation of the hardware thread/hardware resource using an inter-thread communication protocol. A master hardware thread may be configured to communicate status requests to associated slave hardware threads and/or hardware resources. Each slave hardware thread/hardware resource may be configured with hardware logic configured to automatically determine status information for the slave hardware thread/hardware resource and communicate a status response to the master hardware thread independent of the operation of the slave hardware thread/hardware resource.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: February 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer
  • Direct interthread communication dataport pack/unpack and load/save
    Patent number: 9251116
    Abstract: A circuit arrangement, method, and program product for compressing and decompressing data in a node of a system including a plurality of nodes interconnected via an on-chip network. Compressed data may be received and stored at an input buffer of a node, and in parallel with moving the compressed data to an execution register of the node, decompression logic of the node may decompress the data to generate uncompressed data, such that uncompressed data is stored in the execution register for utilization by an execution unit of the node. Uncompressed data may be output by the execution unit into the execution register, and in parallel with moving the uncompressed data to an output buffer of the node connected to the on-chip network, compression logic may compress the uncompressed data to generate compressed data, such that compressed data is stored at the output buffer.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Cache swizzle with inline transposition
    Patent number: 9244840
    Abstract: A method and circuit arrangement selectively swizzle data in one or more levels of cache memory coupled to a processing unit based upon one or more swizzle-related page attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a memory access request for data in a memory page, such that attributes associated with the memory page in the data structure may be used to control whether data is swizzled, and if so, how the data is to be formatted in association with handling the memory access request.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer
  • Cache swizzle with inline transposition
    Patent number: 9239791
    Abstract: A method and circuit arrangement selectively swizzle data in one or more levels of cache memory coupled to a processing unit based upon one or more swizzle-related page attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a memory access request for data in a memory page, such that attributes associated with the memory page in the data structure may be used to control whether data is swizzled, and if so, how the data is to be formatted in association with handling the memory access request.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer
  • FLOATING POINT EXECUTION UNIT FOR CALCULATING PACKED SUM OF ABSOLUTE DIFFERENCES
    Publication number: 20150370557
    Abstract: A method provides support for packed sum of absolute difference operations in a floating point execution unit, e.g., a scalar or vector floating point execution unit. Existing adders in a floating point execution unit may be utilized along with minimal additional logic in the floating point execution unit to support efficient execution of a fixed point packed sum of absolute differences instruction within the floating point execution unit, often eliminating the need for a separate vector fixed point execution unit in a processor architecture, and thereby leading to less logic and circuit area, lower power consumption and lower cost.
    Type: Application
    Filed: August 27, 2015
    Publication date: December 24, 2015
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • SHARED RECEIVE QUEUE ALLOCATION FOR NETWORK ON A CHIP COMMUNICATION
    Publication number: 20150370736
    Abstract: A method for communicating data in a processing architecture comprising a plurality of interconnected IP blocks. Transmitting IP blocks may transmit messages to a shared receive queue for a first IP block. Receipt of the messages at the shared receive queue may be controlled based on receive credits allocated to each transmitting IP block. The allocation of receive credits for each transmitting IP block may dynamically managed such that the allocation of receive credits may be dynamically adjusted for each transmitting IP block based at least in part on message traffic associated with each transmitting IP block and/or a priority associated with each transmitting IP block.
    Type: Application
    Filed: August 27, 2015
    Publication date: December 24, 2015
    Inventors: Jeffrey D. Brown, Robert A. Shearer
  • INSTRUCTION SET ARCHITECTURE WITH OPCODE LOOKUP USING MEMORY ATTRIBUTE
    Publication number: 20150370566
    Abstract: A method decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded.
    Type: Application
    Filed: August 28, 2015
    Publication date: December 24, 2015
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • THREAD SCHEDULING ACROSS HETEROGENEOUS PROCESSING ELEMENTS WITH RESOURCE MAPPING
    Publication number: 20150370609
    Abstract: A method for scheduling processes of a workload on a plurality of hardware threads configured in a plurality of processing elements of a multithreading parallel computing system for processing thereby. Process dimensions for each process are determined based on processing attributes associated with each process, and a place and route algorithm is utilized to map the processes to a processor space representative of the processing resources of the computing system based at least in part on the process dimensions to thereby distribute the processes of the workload.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 24, 2015
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer
  • Chip level power reduction using encoded communications
    Patent number: 9218039
    Abstract: A circuit arrangement, method, and program product communicate data over a communication bus by selectively encoding data values queued for communication over the communication bus based at least in part on at least one data value queued to be communicated thereafter and at least one previously communicated encoded data value to reduce bit transitions for communication of the encoded data values. By reducing bit transitions in the data communicated over the communication bus, power consumption by the communication bus is likewise reduced.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: December 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores
    Patent number: 9195443
    Abstract: A compiler may optimize source code and any referenced libraries to execute on a plurality of different processor architecture implementations. For example, if a compute node has three different types of processors with three different architecture implementations, the compiler may compile the source code and generate three versions of object code where each version is optimized for one of the three different processor types. After compiling the source code, the resultant executable code may contain the necessary information for selecting between the three versions. For example, when a program loader assigns the executable code to the processor, the system determines the processor's type and ensures only the optimized version that corresponds to that type is executed. Thus, the operating system is free to assign the executable code to any of the different types of processors.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer
  • Power reduction by minimizing bit transitions in the hamming distances of encoded communications
    Patent number: 9189051
    Abstract: A circuit arrangement, method, and program product communicate data over a communication bus by selectively encoding data values queued for communication over the communication bus based at least in part on at least one data value queued to be communicated thereafter and at least one previously communicated encoded data value to reduce bit transitions for communication of the encoded data values. By reducing bit transitions in the data communicated over the communication bus, power consumption by the communication bus is likewise reduced.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: November 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Instruction set architecture with secure clear instructions for protecting processing unit architected state information
    Patent number: 9183399
    Abstract: A method and circuit arrangement utilize secure clear instructions defined in an instruction set architecture (ISA) for a processing unit to clear, overwrite or otherwise restrict unauthorized access to the internal architected state of the processing unit in association with context switch operations. The secure clear instructions are executable by a hypervisor, operating system, or other supervisory program code in connection with a context switch operation, and the processing unit includes security logic that is responsive to such instructions to restrict access by an operating system or process associated with an incoming context to architected state information associated with an operating system or process associated with an outgoing context.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: November 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Combined cache inject and lock operation
    Patent number: 9176885
    Abstract: A circuit arrangement and method utilize cache injection logic to perform a cache inject and lock operation to inject a cache line in a cache memory and automatically lock the cache line in the cache memory in parallel with communication of the cache line to a main memory. The cache injection logic may additionally limit the maximum number of locked cache lines that may be stored in the cache memory, e.g., by aborting a cache inject and lock operation, injecting the cache line without locking, or unlocking and/or evicting another cache line in the cache memory.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer, III
  • Translation management instructions for updating address translation data structures in remote processing nodes
    Patent number: 9170954
    Abstract: Translation management instructions are used in a multi-node data processing system to facilitate remote management of address translation data structures distributed throughout such a system. Thus, in multi-node data processing systems where multiple processing nodes collectively handle a workload, the address translation data structures for such nodes may be collectively managed to minimize translation misses and the performance penalties typically associated therewith.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: October 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Instruction set architecture with secure clear instructions for protecting processing unit architected state information
    Patent number: 9147078
    Abstract: A method and circuit arrangement utilize secure clear instructions defined in an instruction set architecture (ISA) for a processing unit to clear, overwrite or otherwise restrict unauthorized access to the internal architected state of the processing unit in association with context switch operations. The secure clear instructions are executable by a hypervisor, operating system, or other supervisory program code in connection with a context switch operation, and the processing unit includes security logic that is responsive to such instructions to restrict access by an operating system or process associated with an incoming context to architected state information associated with an operating system or process associated with an outgoing context.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Power distribution management in a system on a chip
    Patent number: 9134778
    Abstract: A method, circuit arrangement, and program product for dynamically reallocating power consumption at a component level of a processor. Power tokens representative of a power consumption metric are allocated to interconnected IP blocks of the processor, and as additional power is required by an IP block to perform assigned operations, the IP block may communicate a request for additional power tokens to one or more interconnected IP blocks. The interconnected IP blocks may grant power tokens for the request based on a priority, availability, and/or power consumption target. The requesting IP block may modify power consumption based on power tokens granted by interconnected IP blocks for the request.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: September 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer