Patents by Inventor Robert A. Street

Robert A. Street has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180353284
    Abstract: A neural modulation system includes neural encoder in a patient-external device. The neural encoder converts input signals into a neural stimulation pattern and wirelessly transmits the neural stimulation pattern to a patient-internal device. The patient internal device includes a flexible substrate and a two dimensional array of neural probes disposed on the flexible substrate. Each neural probe includes an array of magnetic neural stimulators and/or an array of neural sensors along with probe addressing circuitry that allow for addressing the magnetic neural stimualtors and/or neural sensors. Control circuitry in the implantable device controls activation of the magnetic neural stimulators and/or neural sensors according to the neural stimulation pattern via the probe addressing circuitry.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 13, 2018
    Inventors: Bernard D. Casse, George Daniel, Jonathan Rivnay, Christopher Paulson, Robert Street
  • Publication number: 20180353283
    Abstract: An implantable subsystem includes multiple implantable neural probes disposed on a flexible substrate. Each neural probe is configured to magnetically stimulate brain neurons. Each probe includes an array of magnetic neural stimulators that magnetically stimulate neurons. Each probe also includes neural probe activation circuitry comprising thin film switches disposed on the flexible substrate. The thin film switches are electrically coupled to row and column activation lines and selectively activate the magnetic neural stimulators in response to neural stimulation activation signals carried on the activation lines.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 13, 2018
    Inventors: Bernard D. Casse, George Daniel, Jonathan Rivnay, Christopher Paulson, Robert Street
  • Publication number: 20180254302
    Abstract: A method and system utilizes ink jetting or printing of surface work function modification material or solution to form modified p-type and/or n-type electrodes. The proposed method is suitable for making complementary OTFT circuits in roll-to-roll fabrication environment.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 6, 2018
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Ping Mei, Robert A. Street, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Publication number: 20180252659
    Abstract: A printed resistive gas detector configuration that is simple, inexpensive and compact, fabricated for incorporation into an electronic device, such as an electronic computing and/or communication device, the printed resistive gas detector configuration designed to continuously monitor for predetermined types of gasses. The printed resistive gas detector configuration manufactured by the use of printing technology to print on a flexible substrate.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 6, 2018
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Robert A. Street, David Eric Schwartz, Ping Mei, Brent S. Krusor, Jonathan Rivnay, Yong Zhang, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Patent number: 9952082
    Abstract: The level sensor system includes a level sensor label configured to be associated with a container containing a material whose level is to be sensed, the level sensor label arrangement having a circuit which includes an inductive element electrically connected to a capacitive structure configured to be associated with the container.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 24, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: David E. Schwartz, Yunda Wang, Robert A. Street, Ping Mei, Janos Veres, Gregory L. Whiting, Steven E. Ready, Tse Nga Ng
  • Publication number: 20170328761
    Abstract: The level sensor system includes a level sensor label configured to be associated with a container containing a material whose level is to be sensed, the level sensor label arrangement having a circuit which includes an inductive element electrically connected to a capacitive structure configured to be associated with the container.
    Type: Application
    Filed: May 10, 2016
    Publication date: November 16, 2017
    Applicant: Palo Alto Research Center Incorporated
    Inventors: David E. Schwartz, Yunda Wang, Robert A. Street, Ping Mei, Janos Veres, Gregory L. Whiting, Steven E. Ready, Tse Nga Ng
  • Patent number: 9539736
    Abstract: A mechanical method for producing micro-scale and nano-scale textures that facilitates, for example, the cost-effective production of nanostructures on large-scale substrates, e.g., during the large-scale production of thin-film solar cells. A “scratcher” (multi-pointed abrasion mechanism) is maintained in a precise position relative to a target substrate such that micron-level features (protrusions) extending from the scratcher's base structure are precisely positioned to contact a surface material layer of the target substrate with a predetermined amount of force, and then moved relative to the substrate (e.g., by way of a conveying mechanism) while maintaining the pressing force such that the micron-level features define elongated parallel nano-scale grooves and/or form nano-scale ridges in the surface material layer (i.e., by mechanically displacing) portions of the surface material layer to form the nano-scale grooves/ridges).
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: January 10, 2017
    Assignee: Palo Alto Research Center Incorporated
    Inventors: David Eric Schwartz, Matthew D. Eisaman, Sourobh Raychaudhuri, Philipp H. Schmaelzle, Robert A. Street, Sean Garner, Baomin Xu, Jiye Lee
  • Publication number: 20160173834
    Abstract: A polarization-sensitive imager, include a polarization filter, the polarization filter including a first region and a second region, a pixel array of light sensors coupled to the polarization filter, the pixel array of light sensors including a first region associated with the first region of the polarization filter and a second region associated with the second region of the polarization filter, each region of the pixel array of light sensors configured to output a signal based on an amount of light illuminated on the region and a processor configured to simultaneously determine an intensity image and a polarization image by taking a sum and difference of the signal of the first region of the pixel array of lights sensors and the signal of the second region of the pixel array of light sensors.
    Type: Application
    Filed: December 15, 2014
    Publication date: June 16, 2016
    Inventors: Julie Bert, Robert A. Street, Sourobh Raychaudhuri
  • Patent number: 9263124
    Abstract: A ultra-violet sensor has a gate on a substrate, a dielectric formed over the gate and the substrate, an oxide semiconductor formed over the dielectric, and a source electrode and a drain electrode formed at the edges of the oxide semiconductor. A memory device has an array of ultra-violet sensors, each sensor having a gate on a substrate, a dielectric formed over the gate and the substrate, an oxide semiconductor formed over the dielectric, and a source electrode and a drain electrode formed at the edges of the oxide semiconductor, an array of ultra-violet light sources corresponding to the array of ultra-violet sensors, an array of detectors electrically coupled to the array of ultra-violet sensors, driving circuitry attached to the array of sensors and the ultra-violet light sources to allow addressing of the arrays, and a reset mechanism.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: February 16, 2016
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Rene A. Lujan, Tse Nga Ng, Robert A. Street
  • Publication number: 20150170738
    Abstract: A ultra-violet sensor has a gate on a substrate, a dielectric formed over the gate and the substrate, an oxide semiconductor formed over the dielectric, and a source electrode and a drain electrode formed at the edges of the oxide semiconductor. A memory device has an array of ultra-violet sensors, each sensor having a gate on a substrate, a dielectric formed over the gate and the substrate, an oxide semiconductor formed over the dielectric, and a source electrode and a drain electrode formed at the edges of the oxide semiconductor, an array of ultra-violet light sources corresponding to the array of ultra-violet sensors, an array of detectors electrically coupled to the array of ultra-violet sensors, driving circuitry attached to the array of sensors and the ultra-violet light sources to allow addressing of the arrays, and a reset mechanism.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 18, 2015
    Applicant: Palo Alto Research Center Incorporated
    Inventors: RENE A. LUJAN, TSE NGA NG, ROBERT A. STREET
  • Patent number: 9035673
    Abstract: A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: May 19, 2015
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Michael Yu Tak Young, Scott Jong Ho Limb, William S. Wong, Robert A. Street
  • Patent number: 8872224
    Abstract: A low-cost neutron detector is formed on a substrate includes a sensor formed by an active material layer sandwiched between two electrodes, and a neutron capture layer formed in close proximity to (i.e., over and/or under) the sensor. The sensor active material layer includes a bulk heterojunction or bilayer structure that is formed by depositing particulate solutions incorporating at least one type of high atomic number nanoparticle using low-temperature (i.e., below 400° C.) solution processing techniques. The sensor electrode material and neutron capture material are similarly disposed in associated solutions (e.g., conductive inks) that are also deposited using low-temperature solution processing techniques, whereby the fabrication process can be carried out on low-cost flexible substrate material (e.g., PET) using high efficiency roll-to-roll production techniques.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 28, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Gregory L. Whiting, Tse Nga Ng, Janos Veres, Robert A. Street
  • Patent number: 8854403
    Abstract: Systems and methods are described that facilitate using TFT control of electronic discharge for surface potential reduction and latent image formation on an imaging member. Corona charging is performed to first create a background surface potential, followed by selective discharge of individual pixels using an array of TFTs to supply free charge carriers to reduce the electrostatic surface potential to nearly zero. This is followed by discharged area development (DAD) to develop the latent image on a print medium (e.g., paper). The described systems and methods do not require a HVPS to drive the backplane; therefore, the TFT matrix is electrostatically decoupled from the developer and other system components in direct contact with the imaging member. Accordingly, known addressing systems may be used to address the TFT array.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: October 7, 2014
    Assignee: Xerox Corporation
    Inventors: Vladislav Skorokhod, Gregory McGuire, Robert A. Street
  • Publication number: 20140264436
    Abstract: A low-cost neutron detector is formed on a substrate includes a sensor formed by an active material layer sandwiched between two electrodes, and a neutron capture layer formed in close proximity to (i.e., over and/or under) the sensor. The sensor active material layer includes a bulk heterojunction or bilayer structure that is formed by depositing particulate solutions incorporating at least one type of high atomic number nanoparticle using low-temperature (i.e., below 400° C.) solution processing techniques. The sensor electrode material and neutron capture material are similarly disposed in associated solutions (e.g., conductive inks) that are also deposited using low-temperature solution processing techniques, whereby the fabrication process can be carried out on low-cost flexible substrate material (e.g., PET) using high efficiency roll-to-roll production techniques.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Gregory L. Whiting, Tse Nga Ng, Janos Veres, Robert A. Street
  • Patent number: 8796112
    Abstract: A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: August 5, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: William S. Wong, Brent S. Krusor, Robert A. Street
  • Patent number: 8766367
    Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 1, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Robert A. Street
  • Patent number: 8673750
    Abstract: A method can include depositing a thin metal film on a substrate of a sample, establishing a metal island on the substrate by patterning the thin metal film, and annealing the sample to de-wet the metal island and form a metal droplet from the metal island. The method can also include growing a nanowire on the substrate using the metal droplet as a catalyst, depositing a thin film of a semiconductor material on the sample, annealing the sample to allow for lateral crystallization to form a crystal grain, and patterning the crystal grain to establish a crystal island. An electronic device can be fabricated using the crystal island.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: March 18, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Robert A. Street, Sourobh Raychaudhuri
  • Patent number: 8674281
    Abstract: A solar energy harvesting system including a luminescent solar concentrator for generating light emissions in response to received sunlight, and for redirecting and concentrating the light emissions onto a predetermined target (e.g., a PV cell). The luminescent solar concentrator includes a light-guiding slab containing a luminescent material that generates the light emissions, spaced-apart outcoupling structures that provide a distributed outcoupling of the light emissions through predetermined locations on one of the “broadside” (e.g., upper or lower) surfaces of the light-guiding slab, and optical elements positioned to redirect the outcoupled light emissions such that the light emissions are concentrated onto the predetermined target.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: March 18, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Philipp H. Schmaelzle, Robert A. Street
  • Publication number: 20140041504
    Abstract: A mechanical method for producing micro-scale and nano-scale textures that facilitates, for example, the cost-effective production of nanostructures on large-scale substrates, e.g., during the large-scale production of thin-film solar cells. A “scratcher” (multi-pointed abrasion mechanism) is maintained in a precise position relative to a target substrate such that micron-level features (protrusions) extending from the scratcher's base structure are precisely positioned to contact a surface material layer of the target substrate with a predetermined amount of force, and then moved relative to the substrate (e.g., by way of a conveying mechanism) while maintaining the pressing force such that the micron-level features define elongated parallel nano-scale grooves and/or form nano-scale ridges in the surface material layer (i.e., by mechanically displacing) portions of the surface material layer to form the nano-scale grooves/ridges).
    Type: Application
    Filed: August 7, 2012
    Publication date: February 13, 2014
    Applicant: Palo Alto Research Center Incorporated
    Inventors: David Eric Schwartz, Matthew D. Eisaman, Sourobh Raychaudhuri, Philipp H. Schmaelzle, Robert A. Street, Sean Garner, Baomin Xu, Jiye Lee
  • Patent number: 8643685
    Abstract: Systems and methods are described that facilitate eliminating a need for a raster output scanner (ROS) or laser when generating a latent image on a photoreceptor. An addressable backplane is employed, comprising an array of field effect transistors (e.g., silicon or organic thin film transistors, or TFTs), wherein each TFT corresponds to a single pixel on a charge transport layer on the photoreceptor surface. Latent image formation is performed by forming a surface potential using corona charging, and then directing free charge carriers toward the photoreceptor surface to reduce electrostatic potential in areas that need to be toned. TFTs in the array are individually addressed, or selected, to connect to a common ground, which allows photodischarge to occur only in selected areas (e.g., pixels associated with the selected TFTs).
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: February 4, 2014
    Assignee: Xerox Corporation
    Inventors: Gregory McGuire, Vladislav Skorokhod, Robert A. Street