Abstract: A luminescent solar concentrator including a light-guiding slab containing a luminescent material that generates light emissions in response to received sunlight, spaced-apart outcoupling structures that provide a distributed outcoupling of the light emissions through predetermined locations on one of the “broadside” (e.g., upper or lower) surfaces of the light-guiding slab, and optical elements positioned to redirect the outcoupled light emissions such that the light emissions are concentrated onto a predetermined target (e.g., a PV cell). Each optical element includes a collimating surface portion and optional returner surface.

Abstract: A solar energy harvesting system including a luminescent solar concentrator for generating light emissions in response to received sunlight, and for redirecting and concentrating the light emissions onto a predetermined target (e.g., a PV cell). The luminescent solar concentrator includes a light-guiding slab containing a luminescent material that generates the light emissions, spaced-apart outcoupling structures that provide a distributed outcoupling of the light emissions through predetermined locations on one of the “broadside” (e.g., upper or lower) surfaces of the light-guiding slab, and optical elements positioned to redirect the outcoupled light emissions such that the light emissions are concentrated onto the predetermined target.

Abstract: A method is used to form a self-aligning thin film transistor. The thin film transistor includes a gate contact formed with a state-switchable material, and a dielectric layer to isolate the gate contact. A source-drain layer, which includes a source contact, and a drain contact are formed with a source-drain material. An area of the gate contact is exposed to a form of energy, wherein the energy transforms a portion of the state switchable material from a non-conductive material to a conductive material, the conductive portion defining the gate contact. A semiconductor material is formed between the source contact and the drain contact.

Abstract: A method of forming a three-dimensional electronic device includes forming an array of pixels on a flexible two-dimensional surface, the array being formed according to a three-dimensional structure, the pixels having addressing lines accessible from at least one edge of the array, cutting the two-dimensional surface, the cuts being located to allow the two-dimensional surface to be shaped, and shaping the two-dimensional surface to form the three-dimensional surface, the array of pixels forming the three-dimensional electronic device. A three-dimensional electronic device has a flexible substrate containing an array of pixels, the substrate fabricated as a flat surface, then cut and shaped to form a three-dimensional surface, the array of pixels covering the three-dimensional surface in subarrays corresponding to segments of the three-dimensional surface, and addressing lines for each subarray being accessible along an edge of the three-dimensional surface.

Abstract: A flexible photovoltaic module has a flexible substrate having integrated electrically conductive portions, an array of functional tiles on the substrate, wherein the functional tiles include solar cell tiles, the functional tiles being separated by a spacing which determines the bending radius of the module, the tiles at least partially in electrical contact with the electrically conductive portions, the solar tiles electrically connected in one of either electrical series or parallel configuration to produce an electrical power output.

Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

Abstract: A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.

Abstract: A compact, optical measurement system has a non-flat detector array having multiple detector elements arranged on a flexible substrate in a monolithic fashion, one or more illumination sources arranged to provide more than one angle of incidence of light on a subject being measured, and a detection system in electrical communication with the detector array, the detection system arranged to receive inputs from the detector array and provide a measurement from the inputs. A method of measuring reflectance of a surface includes placing the surface adjacent a hemispherical detector array, illuminating the surface from a predetermined angle of incidence, simultaneously detecting reflectance at multiple emission angles using the hemispherical detector array, and repeating the illuminating and detecting processes at different angles of incidence. Optional arrays of lenses, baffles and filters may be employed by the system.

Abstract: An organic non-volatile memory array including multiple pixels and associated signal lines that are disposed on and between a substrate, a single ferroelectric dielectric layer, and a single organic dielectric layer, where each pixel includes a ferroelectric field-effect transistor (FeFET) and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of a selected pixel without disturbing the data stored in adjacent pixels. Analog data storage in the FeFET array is also introduced that does not require analog-to-digital conversion of the stored data.

Abstract: A disordered nanowire solar cell includes doped silicon nanowires disposed in a disordered nanowire mat, a thin (e.g., 50 nm) p-i-n coating layer formed on the surface of the silicon nanowires, and a conformal conductive layer disposed on the upper (e.g., n-doped) layer of the p-i-n coating layer. The disordered nanowire mat is grown from a seed layer using VLS processing at a high temperature (e.g., 450° C.), whereby the crystalline silicon nanowires assume a random interwoven pattern that enhances light scattering. Light scattered by the nanowires is absorbed by p-i-n layer, causing, e.g., electrons to pass along the nanowires to the first electrode layer, and holes to pass through the conformal conductive layer to an optional upper electrode layer. Fabrication of the disordered nanowire solar cell is large-area compatible.

Abstract: A display system has an array of display elements on a substrate arranged into a shape having a non-rectangular perimeter, and address lines arranged to transmit signals to the display elements, the address lines conforming at least partially to the non-rectangular perimeter. A display system has an array of display elements arranged on a substrate, the substrate having at least one holes, and address lines arranged on the substrate to address the display elements, the address lines being routed according to the hole.

Abstract: An electronic device comprising a thin film transistor (TFT) array and manufacturing methods thereof according to various embodiments. Jet-printed material is deposited on selected partially formed transistors to form completed transistors. Thus, a selected number of the TFTs are connected into the circuit while the remainder of the TFTs are not connected. An electronic read-out of the array identifies the specific array by distinguishing the connected TFTs from the unconnected ones. For a TFT array with n elements there are 2n alternative configurations; therefore, a relatively small number of TFTs can uniquely identify a huge number of devices. Such uniquely encoded devices have applications for encryption, identification and personalization of electronic systems.

Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.

Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.

Abstract: A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.

Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.

Abstract: A method for patterning fine features using multiple jet-printed etch masks includes forming an initial feature through a first jet-printed etch mask and re-shaping the initial feature through at least one additional jet-printed etch mask.

Abstract: Systems and methods are described that facilitate eliminating a need for a raster output scanner (ROS) or laser when generating a latent image on a photoreceptor. An addressable backplane is employed, comprising an array of field effect transistors (e.g., silicon or organic thin film transistors, or TFTs), wherein each TFT corresponds to a single pixel on a charge transport layer on the photoreceptor surface. Latent image formation is performed by forming a surface potential using corona charging, and then directing free charge carriers toward the photoreceptor surface to reduce electrostatic potential in areas that need to be toned. TFTs in the array are individually addressed, or selected, to connect to a common ground, which allows photodischarge to occur only in selected areas (e.g., pixels associated with the selected TFTs).

Abstract: Systems and methods are described that facilitate using TFT control of electronic discharge for surface potential reduction and latent image formation on an imaging member. Corona charging is performed to first create a background surface potential, followed by selective discharge of individual pixels using an array of TFTs to supply free charge carriers to reduce the electrostatic surface potential to nearly zero. This is followed by discharged area development (DAD) to develop the latent image on a print medium (e.g., paper). The described systems and methods do not require a HVPS to drive the backplane; therefore, the TFT matrix is electrostatically decoupled from the developer and other system components in direct contact with the imaging member. Accordingly, known addressing systems may be used to address the TFT array.