Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

Abstract: Embodiments disclosed herein include an apparatus that comprises a substrate with a component in the substrate, where the component comprises a pad. In an embodiment, a first layer is over the pad, and the first layer comprises silicon and nitrogen. In an embodiment, a second layer is over the substrate, and a via that passes through the first layer and the second layer, where the via contacts the pad.

Abstract: Embodiments disclosed herein include an apparatus that comprises a substrate. In an embodiment, the substrate comprises a glass layer. In an embodiment, a frame is provided around a perimeter of the substrate. In an embodiment, the frame is over a top surface, a bottom surface, and a sidewall surface of the substrate. In an embodiment, the frame comprises a conductive material.

Abstract: Embodiments disclosed herein include an apparatus that includes a substrate that comprises a glass layer. In an embodiment, a frame is provided around the substrate, and a gap is provided between an edge of the substrate and an interior edge of the frame. In an embodiment, a fill layer is provided in the gap, and the fill layer comprises a dielectric material. In an embodiment, a ring is provided over the fill layer around a perimeter of the substrate. In an embodiment, the ring comprises a metallic material.

Abstract: Disclosed herein are microelectronic assemblies including reinforced glass layers, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer, having a first surface and an opposing second surface, and a through-glass via; a first material including a dielectric, a mold, or an epoxy on the first surface; a first conductive via, through the first material, having tapered sides and a smaller cross-section towards the first surface; a first dielectric layer, on the first material, including a first conductive pathway electrically coupled to the first conductive via; a second material including a dielectric, a mold, or an epoxy on the second surface; a second conductive via, through the second material, having tapered sides and a larger cross-section towards the second surface; and a second dielectric layer, on the second material, including a second conductive pathway electrically coupled to the second conductive via.

Abstract: Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Abstract: A microelectronic assembly includes a bridge die embedded in a substrate. The substrate is over a support structure. A via in the substrate between the bridge component and the support structure includes a first end and a second end, where the first end is closer to the support structure than the second end, and the first end has a greater width than a width of the second end. The support structure includes a through-support structure via (TSSV) including a conductive material and a dielectric filler. The TSSV is joined to the via in the substrate.

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

Abstract: Embodiments disclosed herein include components that are embedded within a core of a package substrate. In an embodiment, the component is supported on a pad provided at a bottom of a cavity through the core. In an embodiment, such an apparatus may comprise a substrate with a cavity through a thickness of the substrate. In an embodiment, the cavity comprises sidewalls. In an embodiment, a layer spans an opening of the cavity, and the layer covers at least a portion of the sidewalls of the cavity. In an embodiment, a component is coupled to the layer, and the component is at least partially within the cavity.

Abstract: Systems, apparatus, articles of manufacture, and methods to embed semiconductor devices in cores of package substrates are disclosed. An example package substrate includes a core having a first surface and a second surface. The core includes a cavity extending between the first and second surfaces. The example package substrate further includes a semiconductor die within the cavity; a pedestal within the cavity; and an adhesive within the cavity. The adhesive surrounds the semiconductor die and the pedestal. A material of the pedestal different from a material of the adhesive.

Abstract: Various techniques for alleviating crack formation and propagation in glass cores of microelectronic assemblies, and related devices and methods, are disclosed. The techniques are based on including fillers into glass cores and/or in layers provided on top and/or bottom of glass cores. The fillers have at least one characteristic indicative of material's resistance to breaking under stress being higher than that of glass, which may provide reinforcement and/or increase stiffness of glass, thereby strengthening glass cores. Examples of such characteristics include material strength, fracture toughness, or elastic modulus.

Abstract: Embodiments disclosed herein include package substrates with bridge dies. In an embodiment, an apparatus comprises a first layer that is a glass layer. A via is provided through the first layer, where the via is electrically conductive. In an embodiment, a second layer is over the first layer, and the second layer comprises an organic dielectric material. In an embodiment, a cavity is provided in the second layer, where the via is within a footprint of the cavity. In an embodiment, a die is in the cavity. In an embodiment, the die is electrically coupled to the via.

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (PID) or an organic non-photoimageable dielectric (non-PID); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.