Abstract: In an embodiment, a catheter apparatus includes a catheter and a substantially soluble insertion point extending beyond a distal end of the catheter. The substantially soluble insertion point may be connected to a substantially soluble needle shaft or to a non-soluble needle shaft. The catheter apparatus includes a partial retraction mechanism, in an embodiment, which enables the substantially soluble insertion point to be retracted to a position within the catheter. In other embodiments, the substantially soluble insertion point is fully retractable (i.e., removable) or is non-retractable.

Abstract: In an embodiment, a catheter apparatus includes a catheter tube having a hollow catheter interior, a proximal catheter end, and a distal catheter end. A catheter connector is coupled to the catheter tube at the proximal catheter end. The apparatus further includes a needle having a hollow interior channel, a proximal needle end, and an insertion point. A needle hub is coupled to the needle at the proximal needle end. In an embodiment, the apparatus further includes a retraction mechanism to enable the insertion point to be retracted to a position inside the catheter apparatus.

Abstract: A foam-in-place apparatus includes a foam containment unit, a foam precursor storage unit, and a foam precursor heating unit, in one embodiment. During operation, the foam precursor heating unit is activated to provide activation heat to one or more foam precursor components stored within the foam precursor storage unit. The activation heat may cause temperatures of one or more of the foam precursor components to increase to temperatures within an activation temperature range. The pre-heated component or components are combined to produce an expansive foam, which is deployed in the foam containment unit, and which causes the foam containment unit to expand and displace or contour around any physical objects within the expansion limits of the foam containment unit.

Abstract: A system and method for personalizing cards and other secure identification documents. The card personalizing system and method have improved data integrity, system reliability, and system performance. Improvements to card handling and processing within the modules, improved card transfer between modules, improvements to control of the modules, and other improvements are set forth, all of which contribute, individually and collectively, to achieving these goals.

Abstract: An apparatus functions to immobilize a body part or other physical object. In an embodiment, the apparatus includes a base, one or more flexible bags, and one or more foam precursor packages. In an embodiment, a foam precursor package includes a first chamber, in which a first foam precursor is deployed, and a second chamber, in which a second foam precursor is deployed. The foam precursor package also includes a separation mechanism, which when physically agitated, functions to enable the first and second foam precursors to combine. The combination produces a reaction, which results in the formation of a foam. The foam substantially fills the one or more flexible bags. In an embodiment, a portion of a patient's body is placed in proximity to the apparatus, prior to combination of the precursors. When the foam precursor package is activated, the foam and flexible bags contour around and at least partially immobilize the body part.

Abstract: A system and method for personalizing cards and other secure identification documents. The card personalization system and method provide improved data integrity, system reliability, and system performance. Improvements to card handling and processing within the modules, improved card transfer between modules, improvements to control of the modules, and other improvements are set forth, all of which contribute, individually and collectively, to achieving these goals.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: A game system, incorporating co-existent interaction between a virtual character 20 and a user 10 in the real world, comprising a virtual character 20 in a computer sub-system 12,14 including a computer device 12 and means 38,40,42 for inputting real-world actions of a user in the real world into said sub-system 12,14, whereby actions of a user in the real world, at a pre-chosen real world location 36, other than correlative movements, are recorded and inputted into the computer sub-system and influence the character 20 in the virtual world 16.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store values for reconfiguring the first array of configurable logic blocks, or operate as a RAM. Similarly, the second configuration cache array can either store values for reconfiguring the second array of configurable logic blocks, or operate as a RAM. The first configuration cache memory array and the second configuration cache memory array are independently controlled, such that partial reconfiguration of the FPGA can be accomplished. In addition, the second configuration cache memory array can store values for reconfiguring the first (rather than the second) array of configurable logic blocks, thereby providing a second-level reconfiguration cache memory.

Abstract: A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store values for reconfiguring the first array of configurable logic blocks, or operate as a RAM. Similarly, the second configuration cache array can either store values for reconfiguring the second array of configurable logic blocks, or operate as a RAM. The first configuration cache memory array and the second configuration cache memory array are independently controlled, such that partial reconfiguration of the FPGA can be accomplished. In addition, the second configuration cache memory array can store values for reconfiguring the first (rather than the second) array of configurable logic blocks, thereby providing a second-level reconfiguration cache memory.

Abstract: Dynamic latches for writing to a synchronous RAM are controlled by a clock signal and a delay circuit so that the dynamic latches will not stay in a latched state for more than a selected time interval regardless of the clock signal. One delay circuit limits the length of a write enable signal. Another delay circuit responds to the write enable signal and after a delay returns the address and data latches to their transparent states.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: Dynamic latches for writing to a synchronous RAM are controlled by a clock signal and a delay circuit so that the dynamic latches will not stay in a latched state for more than a selected time interval regardless of the clock signal. One delay circuit limits the length of a write enable signal. Another delay circuit responds to the write enable signal and after a delay returns the address and data latches to their transparent states.

Abstract: The present invention provides a method and apparatus for improving immunity to common mode noise. The present invention prevents common mode noise from exceeding acceptable limits. The present invention is also useful to prevent common mode noise from being converted to differential mode noise by the action of parasitic diodes. One embodiment of the present invention bleeds charge off two differential lines such that the relative voltage differential is maintained, for example during a memory read, until at least one of the lines is low enough that the maximum possible upward noise (common+differential) is insufficient to turn on the parasitic diodes coupled to the positive voltage supply, leaving enough margin on the differential signal to allow a sensing circuit to accurately sense the differential signal.

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration.

Abstract: In accordance with the present invention, a programmable array includes hierarchical configuration and state storage. The array comprises an active storage for an active configuration and an active state as well as an inactive storage for one or more inactive configurations and one or more inactive states. The array further comprises logic and routing configured by the active configuration. The logic includes a plurality of combinational elements and a plurality of sequential logic elements for providing the states. Bits are transferred between the active and the inactive storage.

Abstract: A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a sequential logic element, wherein at least one programmable logic element includes a plurality of memory cells for configuring the combinational element and at least one programmable logic element includes a plurality of memory cells for configuring the sequential logic element. A micro register, which stores a plurality of intermediate states of one CLB or interconnect structure, is located at the output of a CLB, the input of a CLB, or elsewhere in the interconnect structure. The PLD includes means for disabling access to at least one of said plurality of memory elements. In one embodiment, the memory cells are RAM cells, whereas in other embodiments the memory cells are ROM cells, or a combination thereof.