Abstract: An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top surface (49) of the inductor is substantially coplanar with an interconnect surface (31) of the semiconductor substrate, which facilitates connecting to the inductor with standard integrated circuit metallization (57).

Abstract: A muzzle brake for use with a gun includes a cylindrically shaped hollow body having internal threads adjacent the rear end for threadedly attaching the body to the muzzle of the gun adjacent the bore coaxially along a longitudinal axis of the barrel. The body defines an axially extending internal chamber with a flat transverse wall adjacent the forward end. Longitudinally extending, helically shaped slots are formed through the body and in communication with the internal chamber. The slots are equally distributed about the body, and each of the slots has a forward end that is angled generally toward the rear end from an inner periphery of the body to an outer periphery of the body. Each of the slots is further defined by parallel sidewalls defining an opening with an axis offset (non-intersecting) from the longitudinal axis of the barrel.

Abstract: A handguard system for use on a rifle having a barrel and a receiver, the hand guard system includes a barrel nut having an inner surface with a threaded portion adapted to threadably engage the receiver for securing the barrel to the receiver and an outer surface, and a tubular handguard having an end. The tubular handguard is receivable about the barrel and is received about the barrel nut, engaging the outer surface thereof.

Abstract: A semiconductor device (10) includes a semiconductor die (14) having first and second circuit regions (30, 32) formed on a first surface (24). The semiconductor die is housed in a semiconductor package (20) whose lid (40) is formed with a projection (67) that electrically contacts the first surface of the semiconductor die to shield the first circuit region from the second circuit region. Also, inactive components, such as a capacitor can be formed in lid (40).

Abstract: A semiconductor device (10) includes a semiconductor die (14) having first and second circuit regions (30, 32) formed on a first surface (24). The semiconductor die is housed in a semiconductor package (20) whose lid (40) is formed with a projection (67) that electrically contacts the first surface of the semiconductor die to shield the first circuit region from the second circuit region. Also, inactive components, such as a capacitor can be formed in lid (40).

Abstract: An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top surface (49) of the inductor is substantially coplanar with an interconnect surface (31) of the semiconductor substrate, which facilitates connecting to the inductor with standard integrated circuit metallization (57).

Abstract: A method of manufacturing a semiconductor component includes providing a semiconductor substrate (200) having top and bottom surfaces, forming a drain electrode (160) at the bottom surface of the semiconductor substrate (200), and simultaneously forming source and gate electrodes (251, 254, 255, 253) at the first surface of the semiconductor substrate (200).

Abstract: A semiconductor component includes an asymmetric transistor having two lightly doped drain regions (1300, 1701), a channel region (1702), a source region (1916) located within the channel region (1702), a drain region located outside the channel region (1702), a dielectric structure (1404) located over at least one of the two lightly doped drain regions (1300, 1701), two gate electrodes (1902, 1903) located at opposite sides of the dielectric structure (1404), a drain electrode (1901) overlying the drain region (1915), and a source electrode (1904) overlying the source region (1916). The semiconductor component also includes another transistor having an emitter electrode (122) located between a base electrode (121) and a collector electrode (123) where the base electrode (121) is formed over a dielectric structure (1405).

Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying a semiconductor substrate (11). The semiconductor device (10) includes a base region (44) that contacts the corners (13) of the pedestal structure (16). Electrical connection to the base region (44) is provided by a conductive layer (28) that contacts the sides (12) and corners (13) of the pedestal structure (16).

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a dielectric layer (24) to provide electrical isolation. The semiconductor device (10) includes a drain extension region (101) that extend from a drain region (44) to a gate structure (20). The semiconductor device (10) also has a conductive structure (105) that is adjacent to the gate structure (20).

Abstract: A semiconductor component includes an asymmetric transistor having two lightly doped drain regions (1300, 1701), a channel region (1702), a source region (1916) located within the channel region (1702), a drain region located outside the channel region (1702), a dielectric structure (1404) located over at least one of the two lightly doped drain regions (1300, 1701), two gate electrodes (1902, 1903) located at opposite sides of the dielectric structure (1404), a drain electrode (1901) overlying the drain region (1915), and a source electrode (1904) overlying the source region (1916). The semiconductor component also includes another transistor having an emitter electrode (122) located between a base electrode (121) and a collector electrode (123) where the base electrode (121) is formed over a dielectric structure (1405).

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).

Abstract: A method useful in the backside processing of semiconductor wafers includes providing a semiconductor wafer having a first surface that has been substantially processed. The processed first surface of the semiconductor wafer is bonded to a handle wafer. Once bonded to the handle wafer, backside processing may be performed on the wafer. Following backside processing, the wafer is sawn while still bonded to the handle wafer. The individual dice are then removed from the handle wafer. This process involves fewer handling steps of the semiconductor wafer and the handle wafer provides support to the semiconductor wafer during backside processing thereby reducing opportunities for breakage.

Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying an epitaxial layer (12) and a semiconductor substrate (11). The semiconductor device (10) includes a doped region (13) that forms a PN junction with the epitaxial layer (12). The semiconductor device (10) also includes a dielectric layer (22) that has an opening (23) that exposes a portion of the doped region (13) and an opening (24) that exposes a portion of the epitaxial layer (12). The openings (23, 24) are filled with a conductive material (36, 37) to provide contacts (100, 101). Due to the presence of the PN junction, the contacts (100, 101) are capacitively coupled to each other.

Abstract: An SRAM memory cell (40) uses GCMOS transistors (42, 44, 56, and 58) for improving discharge of complementary bit lines (60 and 62). The GCMOS transistors (42, 44, 56, and 58) have a graded-channel region on only the source side of the transistors. Configuring the pass-transistors (56 and 58) having the drain terminals connected to the complementary bit lines (60 and 62) and the cross-coupled transistors (42 and 44) having drain terminals connected to the memory cell outputs improves timing for a read operation of the memory cell (40).

Abstract: An insulated gate semiconductor device (10) having a gate structure (45) that includes a conductive spacer (32) and an extension region (46) extending from the conductive spacer (32). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate dielectric (23) is then formed over the major surface (12) adjacent to the sidewalls (22). The conductive spacer (32) is formed on the gate dielectric (23). The extension region (46) is then formed using selective growth or deposition and patterning of polysilicon adjacent the conductive spacer (32).

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60, 97) that can be used to transport electrical signals across the device (10).

Abstract: A differential amplifier (10) includes three unilateral field effect transistors (12, 14, 16) formed in a common well (40) of a semiconductor material. Each of the three unilateral field effect transistors (12, 14, 16) has an asymmetric channel doping profile. The performance of the differential amplifier (10) is significantly improved by properly orienting the three unilateral field effect transistors (12, 14, 16).

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).