Abstract: A current source with adjustable temperature compensation in which the level of current supplied to a load is adjusted to compensate for the load's inherent change in performance with changes in temperature. The current source allows selection of the appropriate temperature compensating characteristic and operating current solely by altering internal component values.

Abstract: A vertical conducting insulating gate bipolar transistor having an emitter region formed in a base region wherein the base region is not shorted to the emitter is provided. The emitter and base regions are formed in an upper portion of a lightly doped semiconductor drift region and an anode region is formed in a bottom portion of the drift region. During forward conduction, minority carriers are injected from the anode into the base region, biasing the base region sufficiently to inject minority carriers into the upper surface of the drift region. The injected minority carriers improve conductivity in the upper portion of the drift region.

Abstract: A method for protecting a semiconductor power die has been provided. The method involves inserting an integrated circuit die between the gate lead of a package containing the semiconductor power die and the actual gate terminal of the semiconductor power die. As a result, any current flowing into the gate lead of the package must pass through the integrated circuit die before entering the semiconductor power die. This allows the integrated circuit die to monitor and control the semiconductor power die.

Abstract: A semiconductor device having a low source inductance are fabricated by having a maximum of two sources each in contact with a region which makes contact to a substrate or back side of the device. The back side source contact also allows the device to be mounted directly to a grounded heatsink.

Abstract: A method for making a vertical field effect transistor with improved commutating safe operating area is provided a sidewall spacer is formed around a polysilicon gate, and used as a mask for the formation of a low resistivity region. The low resistivity region is formed underneath a source region and extends laterally to within a few thousand angstroms of the lateral boundary of the source region. A central portion of the source region is subsequently removed exposing a portion of the underlying low resistivity region and a source electrode is formed in contact with the exposed low resistivity region and the source region.

Abstract: A low voltage circuit is used to control a high voltage transistor which operates a high voltage motor. A blocking diode and a bootstrap capacitor are used to shift the voltage of the circuit between two levels. The circuit is enabled by inducing a current flow through an input terminal. The current is amplified and applied to a high voltage transistor. The circuit is disabled by termination of the current flow through the input terminal which causes the circuit to rapidly disable current flow through the high voltage transistor. The circuit also disables current flow through the high voltage transistor during voltage transients to prevent erroneous operation during the transients.

Abstract: Integrated high voltage transistors having minimum transistor to transistor crosstalk are fabricated in refilled epitaxial tubs, which are formed in a heavily doped substrate. The heavily doped substrate provides the isolation between each transistor, and thus provides for minimum transistor to transistor crosstalk. The voltage capability of the transistor is increased by forming the base surrounding the collector contact in the refilled epitaxial tub.

Abstract: A high voltage semiconductor structure having multiple guard rings is provided, wherein an enhancement region, which is of an opposite conductivity type from the guard rings, is formed between the guard rings to increase punch-through voltage between the guard rings. A floating field plate ring is formed over each guard ring, capacitively coupled to each guard ring. Each floating field plate has a flap extending beyond the guard ring in the direction of a main PN junction. The floating field plates serve to reduce parasitic coupling between adjacent guard rings.

Abstract: A high voltage semiconductor structure having multiple guard rings, wherein guard rings farthest from a main junction are spaced further from each other than are guard rings closer to the main junction is provided. An enhancement region, which is of an opposite conductivity type from the guard rings, is formed between the guard rings to increase punch-through voltage between the guard rings, thereby increasing the breakdown voltage of the device. The enhancement region and close guard ring spacing result in a fine gradation of electric field and high punch-through breakdown voltage between guard rings.

Abstract: A voltage reference circuit is provided for developing an output voltage operating independent of temperature and power supply variation. A current reference circit provides a current reference signal operating independent of power supply variation and having a predetermined temperature coefficient and flowing through a first transistor and a first resistor each having opposite temperature coefficients. The output voltage is established as the sum of the base-emitter junction potential of the first transistor and the potential developed across the first resistor. The temperature coefficient of the potential developed across the first resistor substantially cancels the temperature coefficient across the base-emitter junction of the first transistor thereby providing the output voltage operating independent of temperature and power supply variation.

Abstract: A thermally protected power transistor comprising a first chip which includes a power transistor and a second chip which includes protection circuitry. The second chip has a plurality of metallic bumps formed thereon which are coupled to various portions of the protection circuitry, wherein at least one metallic bump serves as a thermal couple. The protection circuitry chip is mounted upside down on the power transistor chip and coupled to the power transistor chip by the metallic bumps. The metallic bumps serve to provide electrical power for the protection circuitry, to couple control signals between the protection circuitry and the power transistor, and to couple thermal information from the power transistor to the protection circuitry.

Abstract: A single 3-terminal integrated circuit for controlling a switching device provides both control terminal voltage limitation and rapid turn off time. In an alternative embodiment the control circuit is contained in the same package which houses the controlled switching device.

Abstract: A high voltage bridge interface circuit is provided for AC and brushless DC motor control having a high voltage isolation circuit and drive circuits which simplify the high voltage interface and reduce the total system integration effort. The isolation circuit provides the high voltage unilateral isolation between the control circuit and the high voltage power supply conductors, while the drive circuits improve the noise immunity at the gate termimals of the power MOSFET bridge. The high voltage bridge interface circuit is partitioned by providing the high voltage interface within one IC thereby permitting the integration of the discrete components of the power MOSFET drive circuits and simplifying the overall system integration.

Abstract: An improved method for making a self-aligned vertical field effect transistor is provided wherein a nitride sidewall spacer is formed around a polysilicon gate, and an oxide sidewall spacer, which may be heavily doped with an n-type dopant, is formed covering the silicon nitride sidewall spacer. The silicon nitride sidewall spacer allows the oxide sidewall spacer of a conventional self-aligned vertical field effect transistor process to be removed partially or completely before making ohmic contact to the source thus increasing the contact area between the source and the source electrode and eliminating reliability problems related to n-type doped oxide in contact with aluminum electrodes.

Abstract: An improved means and method is described for forming a Schottky diode integrated with transistors and other devices which is particularly useful where both control circuits and a large power device are on the same chip.Nested N-, P-, N- and P+ regions are formed on an N+ semiconductor substrate. A portion of the overlying dielectric is removed adjacent one of the P+ regions over the N- region and a Schottky contact formed to the N- region and an ohmic contact to the adjacent P+ region. N+ and P+ regions are desirably provided where the junctions between the N-/P- regions and the P-/N- regions intersect the surface to provide contact to the N- and P- regions respectively.A P region extends through the upper N- region and has U-shaped arms which partially overlie an annular shaped P+ region and is located between the active region of the PNP transistor and the collector contact to serve as a Kelvin probe.

Abstract: A propagation delay generator is provided for controlling the duration of a bubble generate waveform of a bubble memory system. A first means is responsive to a digital input signal and provides an initializing signal to a current source. A capacitor is charged, responsive to an R-C time constant, by an increased voltage level prompted by the initializing signal. A second means is responsive to the charging signal in excess of that required to charge the capacitor. The second means thereby provides a digital output that is delayed from the digital input signal.

Abstract: A peak storage amplifier for storing successive peaks of a waveform for a sufficient period of time to insure accurate data transmittal is provided. A differential amplifier is responsive to the waveform and drives a PNP transistor that provides an output. A capacitor stores the peaks of the output waveform as long as a clamp signal is received by a current source that inhibits the current source from sinking the output to ground. Since the PNP transistor is continually reversed biased and the base-collector capacitance is small, the storage capacitor's discharge due to the amplifiers inherent turn-off characteristics is minimized. A compensation capacitor coupled to the differential amplifier prevents the collapse of a Wilson mirror serving as a load to the differential amplifier.

Abstract: A low impedance crossunder region is formed of a low resistivity emitter diffusion within a base region of an active device which extends beneath a portion of a metallization pattern to be crossed. The low resistivity crossunder diffusion is shorted to the base region in order to prevent transistor action between the crossunder region and the base region in contrast with other emitter diffusions within the base region which form diode junctions with the base region.

Abstract: In a voltage boost circuit for use in conjunction with a bubble memory operational driver, an output transistor is alternately turned on and off. When turned on, current flows through an inductor. When turned off, a high voltage is built up across the inductor which causes charge to be transferred to and stored in a capacitor. When the output transistor is turned on so as to permit current to flow through the inductor, a .DELTA.V.sub.BE /R current representative of the current flowing through the output transistor is compared with a .DELTA.V.sub.BE /R reference current. When the first current reaches and exceeds the reference current, the output transistor is turned off.

Abstract: A current ratioing device structure wherein a line of equally spaced emitter regions is parallel to another line of equally spaced base contact portions all within a base region. All of the emitter regions except the first and last emitter region in the line have contact portions so that the first and last emitter regions are "dummy" emitters.