Abstract: Methods, systems, and devices for read threshold adjustment techniques for error recovery are described. A memory system may read a codeword from a memory array using one or more read thresholds. The memory system may increment one or more counters of the memory device based on reading the codeword. The one or more counters may indicate information related to how many bits of the codeword correspond to a particular logic value. The memory system may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory system may adjust the one or more read thresholds based on the information indicated by the one or more counters and read the codeword using the adjusted read thresholds.

Abstract: Methods, systems, and devices for read threshold adjustment techniques for memory are described. A memory device may read a codeword from a memory array of the memory device using a read threshold having a first value. The memory device may increment one or more counters of the memory device based on reading the codeword. The counter may indicate a quantity of bits of the codeword that correspond to a first logic value. The memory device may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory device may adjust the read threshold from the first value to the second value based on the quantity of bits indicated by the counter. The memory device may read the codeword using the read threshold having the second value.

Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.

Abstract: Methods, systems, and devices for error correction for internal read operations are described. In some memory systems, a memory device may perform an internal read operation, in which the memory device reads data internal to the memory device (e.g., without sending the data to a memory system controller). To detect and correct errors during an internal read operation, the memory device may use an error control circuit on a memory die. The error control circuit on the memory die may operate on the same codeword, including the same data and same parity bits, as an error control circuit at the memory system controller, effectively reusing the stored parity bits for host read operations and internal read operations. To reduce the decoding overhead at the memory device, the error control circuit on the memory die may support detecting fewer errors than the error control circuit at the memory system controller.

Abstract: Methods, systems, and devices for read threshold adjustment techniques for error recovery are described. A memory system may read a codeword from a memory array using one or more read thresholds. The memory system may increment one or more counters of the memory device based on reading the codeword. The one or more counters may indicate information related to how many bits of the codeword correspond to a particular logic value. The memory system may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory system may adjust the one or more read thresholds based on the information indicated by the one or more counters and read the codeword using the adjusted read thresholds.

Abstract: Methods, systems, and devices for read threshold adjustment techniques for memory are described. A memory device may read a codeword from a memory array of the memory device using a read threshold having a first value. The memory device may increment one or more counters of the memory device based on reading the codeword. The counter may indicate a quantity of bits of the codeword that correspond to a first logic value. The memory device may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory device may adjust the read threshold from the first value to the second value based on the quantity of bits indicated by the counter. The memory device may read the codeword using the read threshold having the second value.

Abstract: Methods, systems, and devices for read threshold adjustment techniques for error recovery are described. A memory system may read a codeword from a memory array using one or more read thresholds. The memory system may increment one or more counters of the memory device based on reading the codeword. The one or more counters may indicate information related to how many bits of the codeword correspond to a particular logic value. The memory system may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory system may adjust the one or more read thresholds based on the information indicated by the one or more counters and read the codeword using the adjusted read thresholds.

Abstract: Methods, systems, and devices for read threshold adjustment techniques for error recovery are described. A memory system may read a codeword from a memory array using one or more read thresholds. The memory system may increment one or more counters of the memory device based on reading the codeword. The one or more counters may indicate information related to how many bits of the codeword correspond to a particular logic value. The memory system may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory system may adjust the one or more read thresholds based on the information indicated by the one or more counters and read the codeword using the adjusted read thresholds.

Abstract: Methods, systems, and devices for error correction for internal read operations are described. In some memory systems, a memory device may perform an internal read operation, in which the memory device reads data internal to the memory device (e.g., without sending the data to a memory system controller). To detect and correct errors during an internal read operation, the memory device may use an error control circuit on a memory die. The error control circuit on the memory die may operate on the same codeword, including the same data and same parity bits, as an error control circuit at the memory system controller, effectively reusing the stored parity bits for host read operations and internal read operations. To reduce the decoding overhead at the memory device, the error control circuit on the memory die may support detecting fewer errors than the error control circuit at the memory system controller.

Abstract: A memory cell can have a state in a valley between adjacent data states. A determination can be made whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.

Abstract: Methods, systems, and devices for read threshold adjustment techniques for memory are described. A memory device may read a codeword from a memory array of the memory device using a read threshold having a first value. The memory device may increment one or more counters of the memory device based on reading the codeword. The counter may indicate a quantity of bits of the codeword that correspond to a first logic value. The memory device may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory device may adjust the read threshold from the first value to the second value based on the quantity of bits indicated by the counter. The memory device may read the codeword using the read threshold having the second value.

Abstract: A method for performing a copyback procedure is described. The method includes determining to move first encoded data from a first location in a memory die to a second location. In response to determining to move the first encoded data from the first location to the second location, a starting seed, which is associated with the first location, is combined with a destination seed, which is associated with the second location, to produce a combined seed. Based on the combined seed, the method determines a pseudorandom sequence based on the combined seed and a pseudorandom sequence table, wherein the pseudorandom sequence table maps seed values to pseudorandom sequences and the determined pseudorandom sequence maps to the combined seed in the pseudorandom sequence table. The method further combines the first encoded data with the pseudorandom sequence to produce second encoded data for storage in the second location.

Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.

Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.

Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.

Abstract: A method for performing a copyback procedure is described. The method includes determining to move first encoded data from a first location in a memory die to a second location. In response to determining to move the first encoded data from the first location to the second location, a starting seed, which is associated with the first location, is combined with a destination seed, which is associated with the second location, to produce a combined seed. Based on the combined seed, the method determines a pseudorandom sequence based on the combined seed and a pseudorandom sequence table, wherein the pseudorandom sequence table maps seed values to pseudorandom sequences and the determined pseudorandom sequence maps to the combined seed in the pseudorandom sequence table. The method further combines the first encoded data with the pseudorandom sequence to produce second encoded data for storage in the second location.

Abstract: A method for performing a copyback procedure is described. The method includes determining to move first encoded data from a first location in a memory die to a second location. In response to determining to move the first encoded data from the first location to the second location, a starting seed, which is associated with the first location, is combined with a destination seed, which is associated with the second location, to produce a combined seed. Based on the combined seed, the method determines a pseudorandom sequence based on the combined seed and a pseudorandom sequence table, wherein the pseudorandom sequence table maps seed values to pseudorandom sequences and the determined pseudorandom sequence maps to the combined seed in the pseudorandom sequence table. The method further combines the first encoded data with the pseudorandom sequence to produce second encoded data for storage in the second location.

Abstract: A method for performing a copyback procedure is described. The method includes determining to move first encoded data from a first location in a memory die to a second location. In response to determining to move the first encoded data from the first location to the second location, a starting seed, which is associated with the first location, is combined with a destination seed, which is associated with the second location, to produce a combined seed. Based on the combined seed, the method generates a pseudorandom sequence and combines the first encoded data with the pseudorandom sequence to produce second encoded data. In this configuration, the first encoded data is scrambled based on the starting seed while, based on combining the first encoded data with the pseudorandom sequence, the second encoded data is scrambled based on the destination seed. Thereafter, the second encoded data is stored in the second location.

Abstract: A memory cell can have a state in a valley between adjacent data states. A determination can be made whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.

Abstract: A memory cell can have a state in a valley between adjacent data states. A determination can be made whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.