Patents by Inventor Robert B. Eisenhuth
Robert B. Eisenhuth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10740173Abstract: A digital system includes nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of transferring read data and write data relating to the memory, can be changed on a codeword-to-codeword basis based on input parameters.Type: GrantFiled: July 5, 2016Date of Patent: August 11, 2020Assignee: Micron Technology, Inc.Inventors: Robert B. Eisenhuth, Stephen P. Van Aken
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Patent number: 10498367Abstract: A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder.Type: GrantFiled: April 19, 2017Date of Patent: December 3, 2019Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Nicholas Julian Richardson, Patrick Robert Khayat, Mustafa Nazmi Kaynak, Ka Leung Ling, Robert B. Eisenhuth
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Patent number: 10355815Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.Type: GrantFiled: May 20, 2016Date of Patent: July 16, 2019Assignee: Micron Technology, Inc.Inventors: Bruce A. Liikanen, Stephen P. Van Aken, Gerald L. Cadloni, John L. Seabury, Robert B. Eisenhuth
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Publication number: 20180268896Abstract: The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley.Type: ApplicationFiled: May 23, 2018Publication date: September 20, 2018Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Robert B. Eisenhuth
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Patent number: 9990988Abstract: A determination can be made as to whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.Type: GrantFiled: June 10, 2015Date of Patent: June 5, 2018Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Robert B. Eisenhuth
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Publication number: 20170222663Abstract: A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder.Type: ApplicationFiled: April 19, 2017Publication date: August 3, 2017Inventors: Sivagnanam Parthasarathy, Nicholas Julian Richardson, Patrick Robert Khayat, Mustafa Nazmi Kaynak, Ka Leung Ling, Robert B. Eisenhuth
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Patent number: 9654144Abstract: A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder.Type: GrantFiled: September 30, 2014Date of Patent: May 16, 2017Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Nicholas Julian Richardson, Patrick Robert Khayat, Mustafa Nazmi Kaynak, Ka Leung Ling, Robert B. Eisenhuth
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Publication number: 20160314039Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.Type: ApplicationFiled: July 5, 2016Publication date: October 27, 2016Inventors: Robert B. Eisenhuth, Stephen P. Van Aken
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Publication number: 20160269147Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.Type: ApplicationFiled: May 20, 2016Publication date: September 15, 2016Inventors: Bruce A. Liikanen, Stephen P. Van Aken, Gerald L. Cadloni, John L. Seabury, Robert B. Eisenhuth
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Patent number: 9411675Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword-to-codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities can be performed.Type: GrantFiled: November 19, 2013Date of Patent: August 9, 2016Assignee: Micron Technology, Inc.Inventors: Robert B. Eisenhuth, Stephen P. Van Aken
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Patent number: 9374343Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.Type: GrantFiled: December 4, 2013Date of Patent: June 21, 2016Assignee: Micron Technology, Inc.Inventors: Bruce A. Liikanen, Stephen P. Van Aken, Gerald L. Cadloni, John L. Seabury, Robert B. Eisenhuth
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Publication number: 20160094247Abstract: A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder.Type: ApplicationFiled: September 30, 2014Publication date: March 31, 2016Inventors: Sivagnanam Parthasarathy, Nicholas Julian Richardson, Patrick Robert Khayat, Mustafa Nazmi Kaynak, Ka Leung Ling, Robert B. Eisenhuth
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Publication number: 20150310911Abstract: The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley.Type: ApplicationFiled: June 10, 2015Publication date: October 29, 2015Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Robert B. Eisenhuth
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Patent number: 9064575Abstract: The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley.Type: GrantFiled: August 3, 2012Date of Patent: June 23, 2015Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Robert B. Eisenhuth
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Patent number: 8782474Abstract: A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.Type: GrantFiled: August 13, 2013Date of Patent: July 15, 2014Assignee: Micron Technology, Inc.Inventors: Larry J. Koudele, Robert B. Eisenhuth
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Publication number: 20140093076Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.Type: ApplicationFiled: December 4, 2013Publication date: April 3, 2014Applicant: Micron Technology, Inc.Inventors: Bruce A. Liikanen, Stephen P. Van Aken, Gerald L. Cadloni, John L. Seabury, Robert B. Eisenhuth
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Publication number: 20140082454Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.Type: ApplicationFiled: November 19, 2013Publication date: March 20, 2014Applicant: Micron Technology, Inc.Inventors: Robert B. Eisenhuth, Stephen P. Van Aken
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Publication number: 20140036589Abstract: The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley.Type: ApplicationFiled: August 3, 2012Publication date: February 6, 2014Applicant: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Robert B. Eisenhuth
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Patent number: 8627165Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.Type: GrantFiled: March 13, 2009Date of Patent: January 7, 2014Assignee: Micron Technology, Inc.Inventors: Bruce A. Liikanen, Stephen P. Van Aken, Gerald L. Cadloni, John L. Seabury, Robert B Eisenhuth
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Patent number: 8615703Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities can be performed.Type: GrantFiled: June 4, 2010Date of Patent: December 24, 2013Assignee: Micron Technology, Inc.Inventors: Robert B Eisenhuth, Stephen P. Van Aken