Patents by Inventor Robert Briggs

Robert Briggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12367633
    Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.
    Type: Grant
    Filed: March 4, 2024
    Date of Patent: July 22, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
  • Patent number: 12312657
    Abstract: A manufacturing method that includes additively manufacturing a part from an additive manufacturing feedstock comprising a titanium alloy, the titanium alloy comprising: 5.5 to 6.5 wt % aluminum; 3.0 to 4.5 wt % vanadium; 1.0 to 2.0 wt % molybdenum; 0.3 to 1.5 wt % iron; 0.3 to 1.5 wt % chromium; 0.05 to 0.5 wt % zirconium; 0.2 to 0.3 wt % oxygen; maximum of 0.05 wt % nitrogen; maximum of 0.08 wt % carbon; maximum of 0.25 wt % silicon; and balance titanium, wherein a value of an aluminum structural equivalent [Al]eq ranges from 7.5 to 9.5 wt %, and is defined by the following equation: [ Al ] ? eq = [ Al ] + [ O ] × 10 + [ Zr ] / 6 , and wherein a value of a molybdenum structural equivalent [Mo]eq ranges from 6.0 to 8.5 wt %, and is defined by the following equation: [ Mo ] ? eq = [ Mo ] + [ V ] / 1 .5 + [ Cr ] × 1 . 2 ? 5 + [ Fe ] × 2 . 5 .
    Type: Grant
    Filed: January 26, 2024
    Date of Patent: May 27, 2025
    Assignees: The Boeing Company, VSMPO AVISMA Corporation
    Inventors: Natalia Mitropolskaya, Robert Briggs, Catherine Parrish, Arash Ghabchi, Matthew Crill, Michael Leder, Igor Puzakov, Alexey Zaitsev, Natalia Tarenkova
  • Publication number: 20250166276
    Abstract: A control stream decoder decodes a control stream for a tile group comprising at least two tiles of a rendering space. A primitive block entry analyser received a primitive block entry of the control stream and identifies a location in memory of a control data block for a corresponding primitive block. For the received primitive block entry, in response to determining that a current tile is a valid tile for the corresponding primitive block, the control data block for the corresponding primitive block is retrieved from the identified location in memory. An address of the corresponding primitive block in memory is identified from the control data block and primitives of that primitive block relevant for rendering the current tile, and information identifying the address of the corresponding primitive block and the primitives of that primitive block relevant for rendering the current tile is outputted.
    Type: Application
    Filed: January 18, 2025
    Publication date: May 22, 2025
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley
  • Patent number: 12293448
    Abstract: Methods and graphics processing systems render items of geometry using a rendering space which is subdivided into a plurality of first regions. Each of the first regions is sub-divided into a plurality of second regions. Each of a plurality of items of geometry is processed by identifying which of the first regions the item of geometry is present within, and for each identified first region determining an indication of the spatial coverage, within the identified first region, of the item of geometry, and using the determined indication of the spatial coverage within the identified first region to determine whether to add the item of geometry to a first control list for the identified first region or to add the item of geometry to one or more second control lists for a respective one or more of the second regions within the identified first region.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: May 6, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg
  • Publication number: 20250124642
    Abstract: A graphics processing system renders primitives using a rendering space which is sub-divided into a plurality of regions. Geometry processing logic performs a geometry processing phase for a current render wherein for each region in the plurality of regions it is determined, for each of a plurality of primitives which are present in the region, whether the primitive totally covers the region, and total coverage data is stored indicating which of the primitives which are present in the region totally cover the region. Rendering logic performs, after the geometry processing logic has completed the geometry processing phase for the current render, a rendering phase for each of the regions of the plurality of regions on a region-by-region basis for the current render using the total coverage data for the region.
    Type: Application
    Filed: November 26, 2024
    Publication date: April 17, 2025
    Inventors: Xile Yang, Robert Brigg
  • Patent number: 12266044
    Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.
    Type: Grant
    Filed: December 31, 2023
    Date of Patent: April 1, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley
  • Patent number: 12229878
    Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods include receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: February 18, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, John W. Howson
  • Publication number: 20250053324
    Abstract: A set of two or more variable length data blocks is stored in memory. Each variable length data block has a maximum size of N*B, wherein N is an integer greater than or equal to two, and B is a maximum data size that can be written to the memory using a single memory access request. For each variable length data block of the set, the first P non-overlapping portions of size B of the variable length data block are stored in a chunk of the memory allocated to that variable length data block, wherein P is a minimum of (i) a number of non-overlapping portions of size B of the variable length data block and (ii) X which is an integer less than N. Any remaining portions of the variable length data blocks are stored in a remainder section of the memory shared between the variable length data blocks of the set. Information indicating the size of each of the variable length data blocks in the set is stored in a header.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventor: Robert Brigg
  • Patent number: 12211118
    Abstract: A graphics processing system for generating a rendering output includes geometry processing logic having first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block used in generating the rendering output.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: January 28, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John Howson, Xile Yang
  • Patent number: 12154210
    Abstract: Graphics processing renders primitives using a rendering space which is subdivided into a plurality of regions. A geometry processing phase determines, for each of a plurality of primitives which are present in a region, whether the primitive totally covers the region and stores data for the primitives which are determined to totally cover the region to indicate total coverage of the region. A rendering phase retrieves the stored data for the primitives which are present in the region, selectively processes primitives which are present in the region based on the retrieved data to determine which sample points within the region are covered by the primitives, wherein if the retrieved data includes data which indicates total coverage of the region for a particular primitive then the processing determining sample points is skipped; and determines rendered values at the sample points within the region based on the primitives which cover the respective sample points.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: November 26, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg
  • Patent number: 12153814
    Abstract: A set of two or more variable length data blocks is stored in memory. Each variable length data block has a maximum size of N*B, wherein N is an integer greater than or equal to two, and B is a maximum data size that can be written to the memory using a single memory access request. For each variable length data block of the set, the first P non-overlapping portions of size B of the variable length data block are stored in a chunk of the memory allocated to that variable length data block, wherein P is a minimum of (i) a number of non-overlapping portions of size B of the variable length data block and (ii) X which is an integer less than N. Any remaining portions of the variable length data blocks are stored in a remainder section of the memory shared between the variable length data blocks of the set. Information indicating the size of each of the variable length data blocks in the set is stored in a header.
    Type: Grant
    Filed: September 4, 2023
    Date of Patent: November 26, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Robert Brigg
  • Patent number: 12051282
    Abstract: The present invention comprises a system and method of conducting a publicly auditable election using secret ballots. The invention allows an elector to verify their ballot has been counted towards the result of an election in the manner in which it was cast. The elector is capable of cryptographically proving if their ballot has been altered or deleted. Any interested individual or entity is capable of auditing the election using an anonymized database of published ballots.
    Type: Grant
    Filed: May 21, 2022
    Date of Patent: July 30, 2024
    Inventor: Carey Robert Briggs
  • Publication number: 20240240285
    Abstract: A manufacturing method that includes additively manufacturing a part from an additive manufacturing feedstock comprising a titanium alloy, the titanium alloy comprising: 5.5 to 6.5 wt % aluminum; 3.0 to 4.5 wt % vanadium; 1.0 to 2.0 wt % molybdenum; 0.3 to 1.5 wt % iron; 0.3 to 1.5 wt % chromium; 0.05 to 0.5 wt % zirconium; 0.2 to 0.3 wt % oxygen; maximum of 0.05 wt % nitrogen; maximum of 0.08 wt % carbon; maximum of 0.25 wt % silicon; and balance titanium, wherein a value of an aluminum structural equivalent [Al]eq ranges from 7.5 to 9.5 wt %, and is defined by the following equation: [ Al ] ? eq = [ Al ] + [ O ] × 10 + [ Zr ] / 6 , and wherein a value of a molybdenum structural equivalent [Mo]eq ranges from 6.0 to 8.5 wt %, and is defined by the following equation: [ Mo ] ? eq = [ Mo ] + [ V ] / 1 .5 + [ Cr ] × 1 . 2 ? 5 + [ Fe ] × 2 . 5 .
    Type: Application
    Filed: January 26, 2024
    Publication date: July 18, 2024
    Applicants: The Boeing Company, VSMPO-AVISMA Corporation
    Inventors: Natalia Mitropolskaya, Robert Briggs, Catherine Parrish, Arash Ghabchi, Matthew Crill, Michael Leder, Igor Puzakov, Alexey Zaitsev, Natalia Tarenkova
  • Patent number: 12020362
    Abstract: Methods and control stream generators for generating a control stream for a tile group comprising at least two tiles, the control stream identifying primitive blocks that are relevant to rendering at least one tile in the tile group.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: June 25, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
  • Publication number: 20240135625
    Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.
    Type: Application
    Filed: December 31, 2023
    Publication date: April 25, 2024
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley
  • Publication number: 20240104833
    Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods include receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Inventors: Xile Yang, Robert Brigg, John W. Howson
  • Patent number: 11920217
    Abstract: A titanium alloy for additive manufacturing that includes 5.5 to 6.5 wt % aluminum (Al); 3.0 to 4.5 wt % vanadium (V); 1.0 to 2.0 wt % molybdenum (Mo); 0.3 to 1.5 wt % iron (Fe); 0.3 to 1.5 wt % chromium (Cr); 0.05 to 0.5 wt % zirconium (Zr); 0.2 to 0.3 wt % oxygen (O); maximum of 0.05 wt % nitrogen (N); maximum of 0.08 wt % carbon (C); maximum of 0.25 wt % silicon (Si); and balance titanium, wherein a value of an aluminum structural equivalent [Al]eq ranges from 7.5 to 9.5 wt %, and is defined by the following equation: [Al]eq=[Al]+[O]×10+[Zr]/6, and wherein a value of a molybdenum structural equivalent [Mo]eq ranges from 6.0 to 8.5 wt %, and is defined by the following equation: [Mo]eq=[Mo]+[V]/1.5+[Cr]×1.25+[Fe]×2.5.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 5, 2024
    Assignees: The Boeing Company, VSMPO-AVISMA Corporation
    Inventors: Natalia Mitropolskaya, Robert Briggs, Catherine Parrish, Arash Ghabchi, Matthew Crill, Michael Leder, Igor Puzakov, Alexey Zaitsev, Natalia Tarenkova
  • Patent number: 11922566
    Abstract: Methods and coarse depth test logic perform coarse depth testing in a graphics processing system in which a rendering space is divided into a plurality of tiles. A depth range for a tile identifies a depth range based on primitives previously processed. A determination is made based on the depth range for the tile as to whether all or a portion of a primitive is hidden in the tile. If at least a portion of the primitive is not hidden in the tile, a determination is made as to whether the primitive or a primitive fragment thereof has better depth than the primitives previously processed for the tile. If so, the primitive or the primitive fragment is identified as not requiring a read of a depth buffer to perform full resolution depth testing, such that a determination that at least a portion of the primitive is hidden in the tile causes full resolution depth testing not to be performed on at least that portion of the primitive.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: March 5, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Lorenzo Belli, Robert Brigg
  • Patent number: 11922555
    Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: March 5, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
  • Patent number: 11915363
    Abstract: A tag buffer implements a tag buffer stage of a rasterization phase in a tile-based rendering graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated. A buffer stores an identifier that identifies a visible primitive fragment at each sample position of a tile of the plurality of tiles. A look-up table stores an entry for transformed primitive blocks that indicates whether the tag buffer has received information identifying a primitive fragment associated with that transformed primitive block.
    Type: Grant
    Filed: May 28, 2023
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John W. Howson, Xile Yang