Patents by Inventor Robert B. Staszewski

Robert B. Staszewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10594336
    Abstract: A novel and useful time mode analog to digital converter (ADC) that employs injection locking to overcome the nonlinearities of the voltage controlled oscillator (VCO). The oscillator's frequency is modulated using injection locking rather than varying its supply voltage. The oscillator is injection locked with a vector modulated signal, the frequency of which is derived from the oscillator itself. The output of the oscillator is modulated by the input voltage Vin(t). The output of the modulator is at the same frequency as the oscillator with an envelope (i.e. amplitude) determined by Vin(t). This signal is injected back into the oscillator at one or more points. The frequency of the oscillator ?out(t) changes in order to satisfy the Barkhausen criteria for oscillation. Alternatively, each stage of a ring oscillator (RO) incorporates its own mixer (i.e.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: March 17, 2020
    Assignee: University College Dublin
    Inventors: Imran Bashir, Robert B. Staszewski, Filippo Schembari
  • Patent number: 10447285
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 15, 2019
    Inventors: Roman Staszewki, Robert B. Staszewski, Fuqiang Shi
  • Publication number: 20190280709
    Abstract: A novel and useful time mode analog to digital converter (ADC) that employs injection locking to overcome the non-linearities of the voltage controlled oscillator (VCO). The oscillator's frequency is modulated using injection locking rather than varying its supply voltage. The oscillator is injection locked with a vector modulated signal, the frequency of which is derived from the oscillator itself. The output of the oscillator is modulated by the input voltage Vin(t). The output of the modulator is at the same frequency as the oscillator with an envelope (i.e. amplitude) determined by Vin(t). This signal is injected back into the oscillator at one or more points. The frequency of the oscillator ?out(t) changes in order to satisfy the Barkhausen criteria for oscillation. Alternatively, each stage of a ring oscillator (RO) incorporates its own mixer (i.e.
    Type: Application
    Filed: October 6, 2016
    Publication date: September 12, 2019
    Applicant: University College Dublin
    Inventors: Imran Bashir, Robert B. Staszewski, Filippo Schembari
  • Publication number: 20190020349
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 17, 2019
    Inventors: Roman Staszewki, Robert B. Staszewski, Fuqiang Shi
  • Patent number: 10122371
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 6, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Publication number: 20180083644
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Application
    Filed: November 17, 2017
    Publication date: March 22, 2018
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Patent number: 9853649
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: December 26, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Publication number: 20170005666
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 5, 2017
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Patent number: 9473155
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: October 18, 2016
    Assignee: Texas Instruments Incorporated
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Publication number: 20150318861
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Application
    Filed: July 15, 2015
    Publication date: November 5, 2015
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Patent number: 9116769
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Patent number: 9020454
    Abstract: An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 28, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Khurram Waheed, Robert B. Staszewski, Sameh S. Rezeq, Oren E. Eliezer
  • Patent number: 8855236
    Abstract: A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Sameh Rezeq, Dirk Leipold
  • Patent number: 8559579
    Abstract: An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (?fmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: October 15, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Dirk Leipold, John Wallberg
  • Patent number: 8542616
    Abstract: A novel mechanism for simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing. Multiple RF signals, which may be of various wireless standards, are received using one or more shared processing blocks thereby significantly reducing chip space and power requirements. Shared components include local oscillators, analog to digital converters, digital RX processing and digital baseband processing. In operation, multiple RX front end circuits, one for each desired wireless signal, generate a plurality of IF signals that are frequency multiplexed and combined to create a single combined IF signal. The combined IF signal is processed by a shared processing block. Digital baseband processing is performed on each receive signal to generate respective data outputs. Further, simultaneous full-duplex transmission and reception is performed using a single local oscillator.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: September 24, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Khurram Muhammad, Dirk Leipold
  • Patent number: 8463189
    Abstract: A novel and useful apparatus for and method of predistortion calibration and built-in self testing (BIST) of a nonlinear digitally-controlled radio frequency (RF) power amplifier (DPA) using subharmonic mixing. The RF power amplifier output is temporarily coupled into the frequency reference (FREF) input and the phase error samples generated in the phase locked loop (PLL) are then observed and analyzed. The digital predistortion and BIST mechanisms process the phase error samples to calibrate and test the DPA in the transmitter of the Digital RF Processor (DRP). The invention enables the characterization of nonlinearities, the configuration of internal predistortion, as well as the testing of the transmitter's analogRF circuitry, thereby eliminating commonly employed RF performance testing using high-cost test equipment and associated extended test times.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: June 11, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Imran Bashir, Robert B. Staszewski, Oren E. Eliezer
  • Patent number: 8411793
    Abstract: A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: April 2, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Sameh Rezeq, Dirk Leipold
  • Patent number: 8385476
    Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: February 26, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Dirk Leipold
  • Patent number: 8321489
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: November 27, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Patent number: 8306176
    Abstract: System and method for improving a digital PLL's performance by making fine grained adjustments to the loop gain. A preferred embodiment comprises a plurality of loop gain adjustors (such as loop gain adjustors 605, 606, 607, and 608) that can incrementally adjust the loop gain. The incrementally adjusted loop gains are sequentially brought on-line so that the loop gain of the digital PLL is slowly decreased. By slowly decreasing the loop gain, the digital PLL is less perturbed by smaller noise transients that would take time to settle. Hence, the digital PLL can quickly acquire a signal and then decrease its loop gain and hence its bandwidth when it only needs to track a signal. The reduced bandwidth also reduces the overall noise in the digital PLL that is due to the reference noise contribution.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Dirk Leipold, Khurram Muhammad