Patents by Inventor Robert B. Staszewski
Robert B. Staszewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10911056Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.Type: GrantFiled: September 9, 2019Date of Patent: February 2, 2021Assignee: Texas Instruments IncorporatedInventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
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Patent number: 10594336Abstract: A novel and useful time mode analog to digital converter (ADC) that employs injection locking to overcome the nonlinearities of the voltage controlled oscillator (VCO). The oscillator's frequency is modulated using injection locking rather than varying its supply voltage. The oscillator is injection locked with a vector modulated signal, the frequency of which is derived from the oscillator itself. The output of the oscillator is modulated by the input voltage Vin(t). The output of the modulator is at the same frequency as the oscillator with an envelope (i.e. amplitude) determined by Vin(t). This signal is injected back into the oscillator at one or more points. The frequency of the oscillator ?out(t) changes in order to satisfy the Barkhausen criteria for oscillation. Alternatively, each stage of a ring oscillator (RO) incorporates its own mixer (i.e.Type: GrantFiled: October 6, 2016Date of Patent: March 17, 2020Assignee: University College DublinInventors: Imran Bashir, Robert B. Staszewski, Filippo Schembari
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Publication number: 20200007134Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.Type: ApplicationFiled: September 9, 2019Publication date: January 2, 2020Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
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Patent number: 10447285Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.Type: GrantFiled: September 21, 2018Date of Patent: October 15, 2019Inventors: Roman Staszewki, Robert B. Staszewski, Fuqiang Shi
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Publication number: 20190280709Abstract: A novel and useful time mode analog to digital converter (ADC) that employs injection locking to overcome the non-linearities of the voltage controlled oscillator (VCO). The oscillator's frequency is modulated using injection locking rather than varying its supply voltage. The oscillator is injection locked with a vector modulated signal, the frequency of which is derived from the oscillator itself. The output of the oscillator is modulated by the input voltage Vin(t). The output of the modulator is at the same frequency as the oscillator with an envelope (i.e. amplitude) determined by Vin(t). This signal is injected back into the oscillator at one or more points. The frequency of the oscillator ?out(t) changes in order to satisfy the Barkhausen criteria for oscillation. Alternatively, each stage of a ring oscillator (RO) incorporates its own mixer (i.e.Type: ApplicationFiled: October 6, 2016Publication date: September 12, 2019Applicant: University College DublinInventors: Imran Bashir, Robert B. Staszewski, Filippo Schembari
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Publication number: 20190020349Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.Type: ApplicationFiled: September 21, 2018Publication date: January 17, 2019Inventors: Roman Staszewki, Robert B. Staszewski, Fuqiang Shi
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Patent number: 10122371Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.Type: GrantFiled: November 17, 2017Date of Patent: November 6, 2018Assignee: Texas Instruments IncorporatedInventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
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Publication number: 20180083644Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.Type: ApplicationFiled: November 17, 2017Publication date: March 22, 2018Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
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Patent number: 9853649Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.Type: GrantFiled: September 19, 2016Date of Patent: December 26, 2017Assignee: Texas Instruments IncorporatedInventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
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Publication number: 20170005666Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.Type: ApplicationFiled: September 19, 2016Publication date: January 5, 2017Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
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Patent number: 9473155Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.Type: GrantFiled: July 15, 2015Date of Patent: October 18, 2016Assignee: Texas Instruments IncorporatedInventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
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Publication number: 20150318861Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.Type: ApplicationFiled: July 15, 2015Publication date: November 5, 2015Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
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Patent number: 9116769Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.Type: GrantFiled: November 19, 2012Date of Patent: August 25, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
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Patent number: 9020454Abstract: An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.Type: GrantFiled: May 25, 2012Date of Patent: April 28, 2015Assignee: Texas Instruments IncorporatedInventors: Khurram Waheed, Robert B. Staszewski, Sameh S. Rezeq, Oren E. Eliezer
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Patent number: 8855236Abstract: A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.Type: GrantFiled: September 20, 2011Date of Patent: October 7, 2014Assignee: Texas Instruments IncorporatedInventors: Robert B. Staszewski, Sameh Rezeq, Dirk Leipold
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Patent number: 8559579Abstract: An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (?fmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.Type: GrantFiled: July 1, 2011Date of Patent: October 15, 2013Assignee: Texas Instruments IncorporatedInventors: Robert B. Staszewski, Dirk Leipold, John Wallberg
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Patent number: 8542616Abstract: A novel mechanism for simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing. Multiple RF signals, which may be of various wireless standards, are received using one or more shared processing blocks thereby significantly reducing chip space and power requirements. Shared components include local oscillators, analog to digital converters, digital RX processing and digital baseband processing. In operation, multiple RX front end circuits, one for each desired wireless signal, generate a plurality of IF signals that are frequency multiplexed and combined to create a single combined IF signal. The combined IF signal is processed by a shared processing block. Digital baseband processing is performed on each receive signal to generate respective data outputs. Further, simultaneous full-duplex transmission and reception is performed using a single local oscillator.Type: GrantFiled: October 14, 2008Date of Patent: September 24, 2013Assignee: Texas Instruments IncorporatedInventors: Robert B. Staszewski, Khurram Muhammad, Dirk Leipold
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Patent number: 8463189Abstract: A novel and useful apparatus for and method of predistortion calibration and built-in self testing (BIST) of a nonlinear digitally-controlled radio frequency (RF) power amplifier (DPA) using subharmonic mixing. The RF power amplifier output is temporarily coupled into the frequency reference (FREF) input and the phase error samples generated in the phase locked loop (PLL) are then observed and analyzed. The digital predistortion and BIST mechanisms process the phase error samples to calibrate and test the DPA in the transmitter of the Digital RF Processor (DRP). The invention enables the characterization of nonlinearities, the configuration of internal predistortion, as well as the testing of the transmitter's analogRF circuitry, thereby eliminating commonly employed RF performance testing using high-cost test equipment and associated extended test times.Type: GrantFiled: July 31, 2007Date of Patent: June 11, 2013Assignee: Texas Instruments IncorporatedInventors: Imran Bashir, Robert B. Staszewski, Oren E. Eliezer
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Patent number: 8411793Abstract: A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.Type: GrantFiled: April 6, 2011Date of Patent: April 2, 2013Assignee: Texas Instruments IncorporatedInventors: Robert B. Staszewski, Sameh Rezeq, Dirk Leipold
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Patent number: 8385476Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.Type: GrantFiled: April 24, 2002Date of Patent: February 26, 2013Assignee: Texas Instruments IncorporatedInventors: Robert B. Staszewski, Dirk Leipold