Patents by Inventor Robert Blankenship

Robert Blankenship has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190313426
    Abstract: A method performed by a wireless device (WD) comprises receiving a control message. The control message indicating at least a Modulation and Coding Scheme (MCS) and a scaling factor for a downlink shared channel. The scaling factor indicates a value less than 1. The method further comprises determining a transport block size (TBS) based on the MCS and the scaling factor indicated in the control message. A method performed by a network node comprises indicating in a control message at least a Modulation and Coding Scheme (MCS) and a scaling factor for a downlink shared channel. The scaling factor indicating a value less than 1. The method further comprises sending the control message to a User Equipment (UE), the control message enabling determination of a Transport Block Size (TBS) for a shared downlink channel.
    Type: Application
    Filed: October 10, 2018
    Publication date: October 10, 2019
    Inventors: Zhipeng LIN, Robert BALDEMAIR, Yufei BLANKENSHIP, Jung-Fu CHENG, Jingya LI, Xingqin LIN, Ajit NIMBALKER
  • Publication number: 20190301255
    Abstract: A method of cutting a tubular includes providing a rotatable cutting tool in the tubular, the cutting tool having a blade with a cutting structure thereon; extending the blade relative to the cutting tool; rotating the cutting tool relative to the tubular; guiding the cutting structure into contact with the tubular; cutting the tubular using the blade; and limiting extension of the blade.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Inventors: James Robert MILLER, Dan Hugh BLANKENSHIP, Jeremy Lee STONE, David W. TEALE
  • Patent number: 10380600
    Abstract: A computer-implemented method for identifying a problem from unstructured input includes executing on a computer processor the step of identifying context of a problem description from a service support k ticket which adds one or more tags to the service support ticket, each tag corresponding to an end-user symptom within the problem domain. Intent is mapped according to a machine learning model and the one or more tags which identifies a problem and a confidence measure.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joe Bedoun, Tommy Blankenship, Brian Byrne, Nick J. Cerciello, Liz G. Edelson, Morad El Akbani, Donna Griff, Robert M. Lambert, Shawn D. Mohr, Stacy Newsome, Dennis A. Perpetua, Jr., David M. Reynolds, Gary Woodward
  • Patent number: 10380059
    Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Jeff Willey, Robert Blankenship, Jeffrey Swanson
  • Publication number: 20190238262
    Abstract: Systems and methods are provided for deriving channel feedback for a physical channel based on an indication of the number of transmission repetitions. In some embodiments, a method for use in a wireless device for determining channel feedback for a physical channel includes receiving control signaling including an indication of a number of transmission repetitions of the physical channel. The method also includes deriving the channel feedback for the physical channel based on the indication of the number of transmission repetitions, where a code rate corresponding to the channel feedback corresponds to an effective channel code rate of the physical channel occupying a group of physical resources including the number of transmission repetitions. In this way, the wireless device may report channel conditions that are better than the channel conditions corresponding to a single transmission, according to some embodiments.
    Type: Application
    Filed: April 10, 2019
    Publication date: August 1, 2019
    Inventors: Yufei Blankenship, Robert Mark Harrison
  • Patent number: 10326549
    Abstract: Systems and methods are provided for deriving channel feedback for a physical channel based on an indication of the number of transmission repetitions. In some embodiments, a method for use in a wireless device for determining channel feedback for a physical channel includes receiving control signaling including an indication of a number of transmission repetitions of the physical channel. The method also includes deriving the channel feedback for the physical channel based on the indication of the number of transmission repetitions, where a code rate corresponding to the channel feedback corresponds to an effective channel code rate of the physical channel occupying a group of physical resources including the number of transmission repetitions. In this way, the wireless device may report channel conditions that are better than the channel conditions corresponding to a single transmission, according to some embodiments.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 18, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Yufei Blankenship, Robert Mark Harrison
  • Publication number: 20180196774
    Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.
    Type: Application
    Filed: December 22, 2017
    Publication date: July 12, 2018
    Applicant: Intel Corporation
    Inventors: Jeff Willey, Robert Blankenship, Jeffrey Swanson
  • Patent number: 9729309
    Abstract: Embodiments of an invention for securing transmissions between processor packages are disclosed. In one embodiment, an apparatus includes an encryption unit to encrypt first content to be transmitted from the apparatus to a processor package directly through a point-to-point link.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Simon Johnson, Abhishek Das, Carlos Rozas, Uday Savagaonkar, Robert Blankenship, Kiran Padwekar
  • Publication number: 20160088820
    Abstract: A system for clam digging comprising a clam gun and a cart. The cart comprising a set of wheels, a tower, a plate, a lever, and a tether. The lever with a handle and an attachment point at opposite ends and a pivot mechanism in-between the opposite ends, the pivot mechanism coupled to an upper part of the tower. The tether with a first tether end and a second tether end, the first tether end configured for detachably coupling to the attachment point of the lever, wherein the second tether end has a vent hole cover configured for detachably coupling with the tubular handle of the clam gun and covering a vent hole in the tubular handle.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 31, 2016
    Inventors: Robert Blankenship, Chad Blankenship
  • Patent number: 8793404
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 29, 2014
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Publication number: 20140173275
    Abstract: Embodiments of an invention for securing transmissions between processor packages are disclosed. In one embodiment, an apparatus includes an encryption unit to encrypt first content to be transmitted from the apparatus to a processor package directly through a point-to-point link.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Inventors: Simon Johnson, Abhishek Das, Carlos Rozas, Uday Savagaonkar, Robert Blankenship, Kiran Padwekar
  • Publication number: 20130276162
    Abstract: The present invention provides isolated nucleic acids encoding Ch1 d synthase, gene constructs comprising the isolated nucleic acids and cells, chloroplasts, plant tissue and whole plants ectopically expressing cyanobacterial Ch1 d synthase. The invention also provides isolated antibodies prepared using recombinant Ch1 d synthase. The antibodies and gene constructs of the invention are used to produce Ch1 d in organisms that do not normally produce Ch1 d, and to modify Ch1 d level in cyanobacterial cells, such as for modifying environmental host range and photosynthetic capacity of organisms in low light and/or red or far-red or near far-red light environments.
    Type: Application
    Filed: May 20, 2011
    Publication date: October 17, 2013
    Inventors: Robert Blankenship, Min Chen, Robert Willows
  • Patent number: 8555101
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: October 8, 2013
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Patent number: 8549183
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Patent number: 8473642
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 25, 2013
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Patent number: 8447888
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: May 21, 2013
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Publication number: 20120254563
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Patent number: 8230120
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Patent number: 8230119
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Publication number: 20120089750
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Application
    Filed: December 9, 2011
    Publication date: April 12, 2012
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia