Patents by Inventor Robert Blankenship

Robert Blankenship has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7089362
    Abstract: Apparatus having a cache memory including cache lines configured to cache data sent from an input/output device and an eviction mechanism configured to evict data stored in one of the cache lines based on validity state information associated with the data stored in the one cache line. Each cache line has multiple portions, and validity bits are used to track the validity of respective portions of the cache line. The validity bits are set to predefined values responsive to the number of bytes written into the respective portions in one write transaction. The cache line is evicted by the eviction mechanism when the validity bits corresponding to the cache line all have the predefined values. The eviction mechanism is configured to evict the data even if the cache memory is not full.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventors: Kenneth C. Creta, Robert Blankenship, Robert George
  • Publication number: 20060127674
    Abstract: A curable composition including a polymer comprising, as copolymerized units, a monomer having carboxylic acid groups, anhydride groups, or salts thereof, and at least one of certain hydroxyl group-comprising monomers wherein the ratio of the number of equivalents of the carboxylic acid groups, anhydride groups, or salts thereof to the number of equivalents of the hydroxyl groups is from about 1/0.01 to about 1/3, and wherein the carboxylic acid groups, anhydride groups, or salts thereof are neutralized to an extent of less than about 35% with a fixed base is provided. Also provided is a method for treating a substrate with the curable composition and a substrate bearing the cured composition.
    Type: Application
    Filed: February 7, 2006
    Publication date: June 15, 2006
    Inventors: Robert Blankenship, Karl Bromm, Melaney Gappert, Xun Tang, Barry Weinstein
  • Publication number: 20060106153
    Abstract: Nonionic associative thickeners are provided having a nonionic water soluble polymer backbone with at least two pendant polymeric chains attached to the nonionic water soluble polymer backbone. The pendant polymeric chains have terminal chain segments containing polyoxyalkylene units comprising 3 to 6 carbon atoms. The nonionic associative thickeners are useful for modifying the rheology of compositions including aqueous compositions, such as latex containing compositions.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 18, 2006
    Inventors: Robert Blankenship, Barrett Bobsein, Lifeng Zhang
  • Publication number: 20060101183
    Abstract: A technique to broadcast a message across a point-to-point network. More particularly, embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect.
    Type: Application
    Filed: November 8, 2004
    Publication date: May 11, 2006
    Inventors: Keshavan Tiruvallur, Kenneth Creta, Robert Blankenship
  • Publication number: 20060085602
    Abstract: An arrangement is provided for an external agent to initiate data prefetches from a system memory to a cache associated with a target processor, which needs the data to execute a program, in a computing system. When the external agent has data, it may create and issue a prefetch directive. The prefetch directive may be sent along with system interconnection transactions or sent as a separate transaction to devices including the target processor in the system. When receiving and recognizing the prefetch directive, a hardware prefetcher associated with the target processor may issue a request to the system memory to prefetch data to the cache. The target processor can access data in the cache more efficiently than it accesses data in the system memory. Some pre-processing may also be associated with the data prefetch.
    Type: Application
    Filed: October 15, 2004
    Publication date: April 20, 2006
    Inventors: Ramakrishna Huggahalli, Brannon Batson, Raymond Tetrick, Robert Blankenship
  • Publication number: 20050273400
    Abstract: Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.
    Type: Application
    Filed: June 2, 2004
    Publication date: December 8, 2005
    Inventors: Robert Blankenship, Robert Greiner, Herbert Hum, Kenneth Creta, Buderya Acharya
  • Publication number: 20050251611
    Abstract: In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device using the second header information. In one such embodiment, the first header may be a header of a first protocol and the second header may be of a different protocol that is used to tunnel the transaction through the coherent system.
    Type: Application
    Filed: April 27, 2004
    Publication date: November 10, 2005
    Inventors: Kenneth Creta, Robert Blankenship, Sridhar Muthrasanallur, Jasmin Ajanovic
  • Publication number: 20050251612
    Abstract: In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third channel, based upon a type of the incoming transactions. The incoming transactions may be sent by a peer device coupled to the coherent system. By separating the transactions based on type, deadlocks may be avoided.
    Type: Application
    Filed: April 27, 2004
    Publication date: November 10, 2005
    Inventors: Kenneth Creta, Aaron Spink, Robert Blankenship
  • Publication number: 20050251599
    Abstract: In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2n. In various embodiments, such a transaction identifier combined with a source identifier and a home node identifier may form a globally unique transaction identifier.
    Type: Application
    Filed: April 27, 2004
    Publication date: November 10, 2005
    Inventors: Herbert Hum, Aaron Spink, Robert Blankenship
  • Publication number: 20050085560
    Abstract: A process for preparing multi-stage emulsion polymers is provided. The process is capable of producing multi-stage emulsion polymers having low dry-bulk density. These polymers are useful in coating compositions such as paints and paper coatings.
    Type: Application
    Filed: November 8, 2004
    Publication date: April 21, 2005
    Inventors: Robert Blankenship, James Bardman
  • Publication number: 20050080209
    Abstract: The present invention relates to a continuous process for producing polymeric nanoparticles of 1 to 100 nm in diameter comprising continuously feeding a reaction mixture comprising at least one type of monomer into a reactor under reaction conditions capable of causing polymerization of said monomer to produce said polymeric nanoparticles.
    Type: Application
    Filed: October 8, 2003
    Publication date: April 14, 2005
    Inventors: Robert Blankenship, Wayne Devonport, Eric Lundquist
  • Publication number: 20050059748
    Abstract: A process is provided for preparing voided polymer particles. The process includes the emulsion polymerization of multistage polymer particles in a first vessel and the preparation of the voided polymer particles from the multistage polymer particles in a second vessel. Also provided is an aqueous dispersion of voided polymer particles prepared by this process.
    Type: Application
    Filed: September 13, 2004
    Publication date: March 17, 2005
    Inventor: Robert Blankenship
  • Publication number: 20050038193
    Abstract: A curable composition including a polymer comprising, as copolymerized units, a monomer having carboxylic acid groups, anhydride groups, or salts thereof, and at least one of certain hydroxyl group-comprising monomers wherein the ratio of the number of equivalents of the carboxylic acid groups, anhydride groups, or salts thereof to the number of equivalents of the hydroxyl groups is from about 1/0.01 to about 1/3, and wherein the carboxylic acid groups, anhydride groups, or salts thereof are neutralized to an extent of less than about 35% with a fixed base is provided. Also provided is a method for treating a substrate with the curable composition and a substrate bearing the cured composition.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 17, 2005
    Inventors: Robert Blankenship, Karl Bromm, Melaney Gappert, Xun Tang, Barry Weinstein
  • Publication number: 20050014883
    Abstract: The present invention relates to a process for preparing an aqueous polymer dispersion containing polymer particles dispersed in an aqueous medium. The process includes providing first polymer particles; adding a hydrophobic polymerization blocker or a styrenic monomer polymerization blocker to the aqueous medium containing the first polymer particles; and preparing second polymer particles in the presence of the first polymer particles. The aqueous polymer dispersion contain first polymer particles and the second polymer that differ according to at least one attribute such as particle diameter, molecular weight, composition, glass transition temperature, or morphology; or contain polymer particles having a broad polydispersity. The aqueous polymer dispersion prepared by the process of this invention is useful in a wide range of applications, including paints, adhesive, binders for nonwovens, and binders for paper coatings.
    Type: Application
    Filed: July 14, 2004
    Publication date: January 20, 2005
    Inventors: Robert Blankenship, Gary Dombrowski, Ralph Even
  • Patent number: 6681292
    Abstract: A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: January 20, 2004
    Assignee: Intel Corporation
    Inventors: Kenneth C. Creta, Mike Bell, Robert George, Bradford B Congdon, Robert Blankenship, Duane January
  • Publication number: 20030126369
    Abstract: Apparatus having a cache memory including cache lines configured to cache data sent from an input/output device and an eviction mechanism configured to evict data stored in one of the cache lines based on validity state information associated with the data stored in the one cache line. Each cache line has multiple portions, and validity bits are used to track the validity of respective portions of the cache line. The validity bits are set to predefined values responsive to the number of bytes written into the respective portions in one write transaction. The cache line is evicted by the eviction mechanism when the validity bits corresponding to the cache line all have the predefined values. The eviction mechanism is configured to evict the data even if the cache memory is not full.
    Type: Application
    Filed: December 27, 2001
    Publication date: July 3, 2003
    Inventors: Kenneth C. Creta, Robert Blankenship, Robert George
  • Publication number: 20030041212
    Abstract: A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.
    Type: Application
    Filed: August 27, 2001
    Publication date: February 27, 2003
    Inventors: Kenneth C. Creta, D. Michael Bell, Robert George, Bradford Congdon, Robert Blankenship, Duane January