Patents by Inventor Robert Briggs

Robert Briggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135625
    Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.
    Type: Application
    Filed: December 31, 2023
    Publication date: April 25, 2024
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley
  • Publication number: 20240104833
    Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods include receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Inventors: Xile Yang, Robert Brigg, John W. Howson
  • Patent number: 11922555
    Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: March 5, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
  • Patent number: 11922566
    Abstract: Methods and coarse depth test logic perform coarse depth testing in a graphics processing system in which a rendering space is divided into a plurality of tiles. A depth range for a tile identifies a depth range based on primitives previously processed. A determination is made based on the depth range for the tile as to whether all or a portion of a primitive is hidden in the tile. If at least a portion of the primitive is not hidden in the tile, a determination is made as to whether the primitive or a primitive fragment thereof has better depth than the primitives previously processed for the tile. If so, the primitive or the primitive fragment is identified as not requiring a read of a depth buffer to perform full resolution depth testing, such that a determination that at least a portion of the primitive is hidden in the tile causes full resolution depth testing not to be performed on at least that portion of the primitive.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: March 5, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Lorenzo Belli, Robert Brigg
  • Patent number: 11920217
    Abstract: A titanium alloy for additive manufacturing that includes 5.5 to 6.5 wt % aluminum (Al); 3.0 to 4.5 wt % vanadium (V); 1.0 to 2.0 wt % molybdenum (Mo); 0.3 to 1.5 wt % iron (Fe); 0.3 to 1.5 wt % chromium (Cr); 0.05 to 0.5 wt % zirconium (Zr); 0.2 to 0.3 wt % oxygen (O); maximum of 0.05 wt % nitrogen (N); maximum of 0.08 wt % carbon (C); maximum of 0.25 wt % silicon (Si); and balance titanium, wherein a value of an aluminum structural equivalent [Al]eq ranges from 7.5 to 9.5 wt %, and is defined by the following equation: [Al]eq=[Al]+[O]×10+[Zr]/6, and wherein a value of a molybdenum structural equivalent [Mo]eq ranges from 6.0 to 8.5 wt %, and is defined by the following equation: [Mo]eq=[Mo]+[V]/1.5+[Cr]×1.25+[Fe]×2.5.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 5, 2024
    Assignees: The Boeing Company, VSMPO-AVISMA Corporation
    Inventors: Natalia Mitropolskaya, Robert Briggs, Catherine Parrish, Arash Ghabchi, Matthew Crill, Michael Leder, Igor Puzakov, Alexey Zaitsev, Natalia Tarenkova
  • Patent number: 11915299
    Abstract: An embodiment of this disclosure provides an apparatus. The apparatus includes a memory element configured to store a plurality of products and services and a processor. The processor is configured to receive profile information for a user accessing a plurality of video content. The processor is also configured to receive video content information for each of the plurality of video content being accessed by the user in a smart viewer. The video content information identifies at least one category associated with each of the plurality of video content. The processor is also configured to identify one or more of the plurality of products or services based on the profile information and the at least one category of the video content information. The processor is also configured to send the one or more of the plurality of products or services to the smart viewer.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: February 27, 2024
    Assignee: AiBUY Holdco, Inc.
    Inventors: Robert K. Spitz, Todd Downing, Christian Briggs
  • Patent number: 11915363
    Abstract: A tag buffer implements a tag buffer stage of a rasterization phase in a tile-based rendering graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated. A buffer stores an identifier that identifies a visible primitive fragment at each sample position of a tile of the plurality of tiles. A look-up table stores an entry for transformed primitive blocks that indicates whether the tag buffer has received information identifying a primitive fragment associated with that transformed primitive block.
    Type: Grant
    Filed: May 28, 2023
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John W. Howson, Xile Yang
  • Patent number: 11880933
    Abstract: Systems and methods for processing primitive fragments in a rasterization phase of a graphics processing system wherein a rendering space is subdivided into a plurality of tiles. The method includes receiving a plurality of primitive fragments, each primitive fragment corresponding to a pixel sample in a tile; determining whether a depth buffer read is to be performed for hidden surface removal processing of one or more of the primitive fragments; sorting the primitive fragments into a priority queue and a non-priority queue based on the depth buffer read determinations; and performing hidden surface removal processing on the primitive fragments in the priority and non-priority queues wherein priority is given to the primitive fragments in the priority queue.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: January 23, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, Lorenzo Belli
  • Patent number: 11861782
    Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: January 2, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley
  • Publication number: 20230409221
    Abstract: A set of two or more variable length data blocks is stored in memory. Each variable length data block has a maximum size of N*B, wherein N is an integer greater than or equal to two, and B is a maximum data size that can be written to the memory using a single memory access request. For each variable length data block of the set, the first P non-overlapping portions of size B of the variable length data block are stored in a chunk of the memory allocated to that variable length data block, wherein P is a minimum of (i) a number of non-overlapping portions of size B of the variable length data block and (ii) X which is an integer less than N. Any remaining portions of the variable length data blocks are stored in a remainder section of the memory shared between the variable length data blocks of the set. Information indicating the size of each of the variable length data blocks in the set is stored in a header.
    Type: Application
    Filed: September 4, 2023
    Publication date: December 21, 2023
    Inventor: Robert Brigg
  • Publication number: 20230401780
    Abstract: Methods and graphics processing systems render items of geometry using a rendering space which is subdivided into a plurality of first regions. Each of the first regions is sub-divided into a plurality of second regions. Each of a plurality of items of geometry is processed by identifying which of the first regions the item of geometry is present within, and for each identified first region determining an indication of the spatial coverage, within the identified first region, of the item of geometry, and using the determined indication of the spatial coverage within the identified first region to determine whether to add the item of geometry to a first control list for the identified first region or to add the item of geometry to one or more second control lists for a respective one or more of the second regions within the identified first region.
    Type: Application
    Filed: August 29, 2023
    Publication date: December 14, 2023
    Inventors: Xile Yang, Robert Brigg
  • Patent number: 11836849
    Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods comprise: receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: December 5, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, John W. Howson
  • Publication number: 20230377092
    Abstract: Tiling engines and methods for hierarchically tiling a plurality of primitives. A chain of sorting units includes a top level sorting unit followed by lower level sorting units, the top level sorting unit determining which of a plurality of regions of a render space each of the plurality of primitives at least partially falls within. For each such region an identifier of that primitive is stored in a queue. Each of the lower level sorting units selects queues of a preceding sorting unit in the chain to process, and determines which of a plurality of sub-regions of the region associated with that queue each of the primitives at least partially falls within. For each such sub-region an identifier of that primitive is stored in a queue of the lower level sorting unit that is associated with that sub-region. An output unit outputs the primitives identified in the queues of the last lower level sorting unit in the chain on a queue by queue basis.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Robert Brigg, Lorenzo Belli
  • Publication number: 20230351670
    Abstract: Graphics processing renders primitives using a rendering space which is subdivided into a plurality of regions. A geometry processing phase determines, for each of a plurality of primitives which are present in a region, whether the primitive totally covers the region and stores data for the primitives which are determined to totally cover the region to indicate total coverage of the region. A rendering phase retrieves the stored data for the primitives which are present in the region, selectively processes primitives which are present in the region based on the retrieved data to determine which sample points within the region are covered by the primitives, wherein if the retrieved data includes data which indicates total coverage of the region for a particular primitive then the processing determining sample points is skipped; and determines rendered values at the sample points within the region based on the primitives which cover the respective sample points.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 2, 2023
    Inventors: Xile Yang, Robert Brigg
  • Publication number: 20230315645
    Abstract: A method of managing access to a physical memory formed of n memory page frames using a set of virtual address spaces having n virtual address spaces each formed of a plurality p of contiguous memory pages. The method includes receiving a write request to write a block of data to a virtual address within a virtual address space i of the n virtual address spaces, the virtual address defined by the virtual address space i, a memory page j within that virtual address space i and an offset from the start of that memory page j; translating the virtual address to an address of the physical memory using a virtual memory table having n by p entries specifying mappings between memory pages of the virtual address spaces and memory page frames of the physical memory, wherein the physical memory address is defined by: (i) the memory page frame mapped to the memory page j as specified by the virtual memory table, and (ii) the offset of the virtual address; and writing the block of data to the physical memory address.
    Type: Application
    Filed: June 2, 2023
    Publication date: October 5, 2023
    Inventors: Robert Brigg, Lorenzo Belli
  • Publication number: 20230298262
    Abstract: A tag buffer implements a tag buffer stage of a rasterization phase in a tile-based rendering graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated. A buffer stores an identifier that identifies a visible primitive fragment at each sample position of a tile of the plurality of tiles. A look-up table stores an entry for transformed primitive blocks that indicates whether the tag buffer has received information identifying a primitive fragment associated with that transformed primitive block.
    Type: Application
    Filed: May 28, 2023
    Publication date: September 21, 2023
    Inventors: Robert Brigg, John W. Howson, Xile Yang
  • Patent number: 11748010
    Abstract: Methods and systems for storing a set of two or more variable length data blocks in a memory. Each variable length data block having a maximum size of N*B, wherein N is an integer greater than or equal to two, and B is a maximum data size that can be written to the memory using a single memory access request. The methods include: storing, for each variable length data block of the set, the first P non-overlapping portions of size B of the variable length data block in a chunk of the memory allocated to that the variable length data block, wherein P is a minimum of (i) a number of non-overlapping portions of size B of the variable length data block and (ii) X which is an integer less than N; storing any remaining portions of the variable length data blocks in a remainder section of the memory that is shared between the variable length data blocks of the set; and storing, in a header section of the memory, information indicating the size of each of the variable length data blocks in the set.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 5, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Robert Brigg
  • Patent number: 11741656
    Abstract: Methods and graphics processing systems render items of geometry using a rendering space which is subdivided into a plurality of first regions. Each of the first regions is sub-divided into a plurality of second regions. Each of a plurality of items of geometry is processed by identifying which of the first regions the item of geometry is present within, and for each identified first region determining an indication of the spatial coverage, within the identified first region, of the item of geometry, and using the determined indication of the spatial coverage within the identified first region to determine whether to add the item of geometry to a first control list for the identified first region or to add the item of geometry to one or more second control lists for a respective one or more of the second regions within the identified first region.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: August 29, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg
  • Publication number: 20230260074
    Abstract: A graphics processing system for generating a rendering output includes geometry processing logic having first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block used in generating the rendering output.
    Type: Application
    Filed: April 27, 2023
    Publication date: August 17, 2023
    Inventors: Robert Brigg, John Howson, Xile Yang
  • Publication number: 20230252711
    Abstract: Methods and control stream generators for generating a control stream for a tile group comprising at least two tiles, the control stream identifying primitive blocks that are relevant to rendering at least one tile in the tile group.
    Type: Application
    Filed: March 7, 2023
    Publication date: August 10, 2023
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang