Abstract: A chip carrier socket for an electronic-photonic integrated-circuit (EPIC) assembly comprises a carrier bottom and a carrier top configured to mate to the carrier bottom while enclosing the EPIC assembly within an enclosed cavity. The carrier bottom comprises one or more conductive vias passing from a first surface of the carrier bottom to an opposite second surface of the carrier bottom, each conductive via providing electrical connectivity between an electrically conductive pad on the first surface of the carrier bottom and a respective electrically conductive pad, solder ball, or electrically conductive spring on the second surface of the carrier bottom. One or both of the carrier bottom and the carrier top comprises a fluid inlet port and a fluid outlet port. Further, either or both of the carrier bottom and the bottom top comprises an optical via passing from one surface to another of the carrier bottom or carrier top.

Abstract: A radio-frequency three-dimensional electronic-photonic integrated circuit (RF 3D EPIC) comprises a radio-frequency (RF) photonic integrated circuit (PIC) layer, the RF PIC layer comprising, in a single integrated circuit, at least one RF antenna and at least one photonic device coupling the RF antenna to an optical interface, and further comprises an electronic-photonic integrated circuit (EPIC) assembly optically coupled to the optical interface of the RF PIC layer, the EPIC assembly comprising two or more integrated-circuit dies bonded to one another so as to form a die stack, wherein at least one of the two or more integrated-circuit dies comprises one or more integrated photonic devices and wherein each of the two or more integrated-circuit dies is electrically connected to at least one other integrated-circuit die via an electrically conductive through-wafer interconnect or an electrically conductive through-wafer via.