Abstract: A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth.

Abstract: A finFET device can include a high mobility semiconductor material in a fin structure that can provide a channel region for the finFET device. A source/drain recess can be adjacent to the fin structure and a graded composition epi-grown semiconductor alloy material, that includes a component of the high mobility semiconductor material, can be located in the source/drain recess.

Abstract: Methods of fabricating quantum well field effect transistors are provided. The methods may include forming a first barrier layer including a first delta doped layer on a quantum well layer and forming a second barrier layer including a second delta doped layer selectively on a portion of the first barrier layer in a first region of the substrate. The methods may also include patterning the first and second barrier layers and the quantum well layer to form a first quantum well channel structure in the first region and patterning the first barrier layer and the quantum well layer to form a second quantum well channel structure in a second region. The methods may further include forming a gate insulating layer on the first and second quantum well channel structures of the substrate and forming a gate electrode layer on the gate insulating layer.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.

Abstract: A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.

Abstract: In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.

Abstract: In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.

Abstract: A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

Abstract: A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

Abstract: A method of soldering leads to electrical elements, such as resistors, in which a ribbon of solder, having a coating of flux, is sandwiched between a plurality of electrical elements and a plurality of leads. Hydrogen flames then cut the ribbon at points between the electrical elements and also between the leads. The hydrogen flames are then directed at the leads to melt the solder and cause extending portions of the ribbons to be drawn towards the leads.

Abstract: A slurry reclamation system for use with a concrete ready-mix plant which enables 100% reclamation of the constituents of concrete mix returned to the plant site by vehicles.Returned concrete mix is dumped into an inlet hopper having a screw classifier for removing aggregate and coarse sand, and a weired channel enabling gravity flow of the water, cement fines and sand fines constituents into a slurry vessel. The slurry in the vessel naturally separates into clarified water and concentrated slurry, and agitators are provided for periodically stirring up the slurry to maintain the cement fines active. The slurry vessel is sized in such a manner as to guarantee complete consumption of slurry returned during a day's production by the end of the following production day, the volumetric capacity of the vessel being related to the total average volume of water used to produce fresh concrete during a representative production day.