Abstract: A method for fabricating a semiconductor integrated circuit structure having sub-micrometer gate length field effect transistor devices is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. A first insulating layer such as silicon dioxide which is designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a conductive layer, a second silicon dioxide layer, a first silicon nitride layer, a polycrystalline silicon layer and a second nitride layer are formed thereover. The multilayer structure is etched to result in a patterned polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions.

Abstract: A method for fabricating a semiconductor integrated circuit structure having a sub-micrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. These semiconductor regions are designated to contain devices. At least one layer is formed over the device designated regions and etched to result in a patterned layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness sidewall layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness sidewall layer portions of which extend across certain of the device regions. The desired pattern of PN junctions are now formed in the substrate using for example diffusion or ion implantation techniques with the controlled thickness sub-micrometer layer used as a mask.

Abstract: Electrical contacts to diffused regions in a semiconductor substrate are made by a process which reduces the space needed in memory or logic cell layouts. The contacts are made such that they overlap, but are insulated from, adjacent conductors. The contacts are formed in a manner which avoids shorting of the diffused junctions to adjacent structures without being limited by lithographic overlay tolerances.

Abstract: A plurality of cellular shapes for honeycomb structures having cells of uniform size and shape are disclosed having movable expansion joint means built into each individual cell structure, which joints can tolerate large strains without breaking.

Abstract: In the hot forming of TV funnels from molten glass, heat is extracted from the glass in the moil area at a lesser rate than that in adjacent areas by providing relatively thin mold portions in such area and thereby producing more fluid glass which may be formed with lower pressing forces. Further, by reducing the wall thickness of the nose portion of a pressing plunger, internal cooling may be applied to such nose portion during the pressing cycle to cool such nose portion and contract it away from the moil area, and thereby prevent the formation of checks and cracks during plunger withdrawal.

Abstract: A non-volatile read mostly memory cell in a monocrystalline semiconductor body wherein the sensing of the information is achieved by measuring the substrate current.

Abstract: A process for forming holes with precisely controlled dimension and position in monocrystalline silicon wafers wherein the holes are fabricated with vertical sides. In the preferred process, both sides of the silicon body are masked, opposite registered openings made in the masking layers, an impurity introduced through the openings into the body forming low resistivity regions, the body anodically etched through the openings until a porous silicon region is formed completely through the body, and subsequently removing the resultant porous silicon region with a silicon etchant.

Abstract: A Schottky barrier diode having an encircling floating polycrystalline silicon gate which becomes charged upon avalanche breakdown of the diode. The gate is self-aligned with respect to the Schottky barrier diode metal so that the gate uniformly overhangs the depletion area in the semiconductor when the diode is reverse biased. The gate is insulated from the semiconductor material and from the metal by dielectric layers including silicon dioxide and silicon nitride.