Abstract: An electronic device manufacturing system configured to performing, by manufacturing equipment, a first process on a first substrate according to a process recipe, wherein the process recipe comprises a plurality of setting parameters. The system then generates metrology data associated with a plurality of features and inputs the metrology data into one or more Bayesian probabilistic models. The system then receives an output from the one or more Bayesian probabilistic models based on the metrology data and at least one settings parameter of the plurality of setting parameters. The system then updates, based on the output of the one or more Bayesian probabilistic models, the process recipe by modifying at least one setting parameter of the plurality of setting parameters, and performs, by the manufacturing equipment, a second process on a second substrate according to the updated process recipe.

Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.

Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database.

Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.

Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database.

Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.

Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.

Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.

Abstract: A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

Abstract: A method for mask process correction or forming a pattern on a resist-coated reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle, and where the pattern exposure information is modified to lower the calculated sensitivity. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a resist-coated reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle.

Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.

Abstract: A method for fracturing or mask data preparation or proximity effect correction or optical proximity correction or mask process correction is disclosed in which a set of charged particle beam shots is determined that is capable of forming a pattern on a surface, wherein critical dimension (CD) split is reduced through the use of overlapping shots.

Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.

Abstract: A method for mask process correction or forming a pattern on a resist-coated reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle, and where the pattern exposure information is modified to lower the calculated sensitivity. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a resist-coated reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle.

Abstract: A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

Abstract: A method for fracturing or mask data preparation or proximity effect correction or optical proximity correction or mask process correction is disclosed in which a set of charged particle beam shots is determined that is capable of forming a pattern on a surface, wherein critical dimension (CD) split is reduced through the use of overlapping shots.

Abstract: A technique models and simulates the impact of imperfectly patterned via arrays on integrated circuits through the use of hierarchical models and a hierarchical circuit simulator. Through the hierarchical modeling and simulation approach discussed here, far more accurate electrical simulation and verification of networks is enabled for; performance, yield, and reliability. The approach further enables simulation of the effects of via process variations on large-scale circuit response. In an implementation, each via in a layout or in a via array is modeled as having an independent size from other vias based upon calibrated process simulation. The electrical characteristics of independent vias and via arrays are modeled and compiled into a reusable hierarchical distributed resistance via model. Hierarchical simulation is performed using these hierarchical distributed via models and enables more accurate results than traditional approaches.

Abstract: Technique assesses the impact of physical circuit variations, specification parameter variation, or process variations on clock, signal, and power network performance and through a hierarchical modeling and hierarchical Monte Carlo simulation method.

Abstract: A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.

Abstract: A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.