Patents by Inventor Robert C. Pack

Robert C. Pack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7302672
    Abstract: A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: November 27, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Robert C. Pack, Louis Scheffer
  • Patent number: 7249342
    Abstract: A method for generating lithography marks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: July 24, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Robert C. Pack, Louis K. Scheffer
  • Patent number: 7231628
    Abstract: A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: June 12, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Robert C. Pack, Louis K. Scheffer
  • Patent number: 7024638
    Abstract: To increase the writing speed of masks, context information can be used to distinguish the attributes of portions of the mask that are critical from attributes, and portions, that are less critical. By using this information, which may be derived from the design context of the features, the mask can be written at a higher speed without sacrificing the accuracy of the important attributes or features.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: April 4, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Louis K. Scheffer, Kenji Yoshida, Yoshikuni Abe, Aki Fujimura, Robert C. Pack
  • Publication number: 20040133369
    Abstract: A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.
    Type: Application
    Filed: July 14, 2003
    Publication date: July 8, 2004
    Applicant: Cadence Design Systems, Inc.
    Inventors: Robert C. Pack, Louis K. Scheffer
  • Publication number: 20040107412
    Abstract: A method for generating lithography marks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.
    Type: Application
    Filed: July 14, 2003
    Publication date: June 3, 2004
    Applicant: Cadence Design Systems, Inc.
    Inventors: Robert C. Pack, Louis K. Scheffer
  • Patent number: 6562638
    Abstract: A method for determining device yield of a semiconductor device design, includes determining statistics of at least one MOSFET parameter from a gate pattern, and calculating device yield from the at least one MOSFET parameter. The method provides a direct simulation link from device layout to device performance.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: May 13, 2003
    Assignees: Cypress Semiconductor Corp., Cadence Design Systems, Inc., Sequoia Design Systems
    Inventors: Artur Balasinski, Robert C. Pack, Valery Axelrad, Victor Vladimir Boksha