Abstract: Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used, in critical areas. This allows all pull-up transistors and/or all pull-down transistors to be formed from contiguous active areas. The D-to-Q path is reduced, and the clock is used to control the output. The clock becomes the dominant controller of the output when it is located closest to the output. Placing the clock devices closest to the clocked nodes reduces clock skew. The rising D response time and falling D response time are caused to be as close as possible to reduce the overall cycle time. To reduce parasitics in the circuit, complex-gates are used which are asymmetric. Even multiples of series branches per gate are used to share contacts and eliminate breaks in the layout diffusion.

Abstract: A cardiac pacer has separate digital filter circuits for sensing atrial and ventricular activity. Parameter data stored in memory is used by the digital filters for identifying the various components of cardiac activity, such as the P, R and T waves, as well as for identifying Premature Ventricular Contractions (PVC). A Ventricular Rate Time Out period is established from the last natural beat or stimulating pulse; and if a P wave or natural R wave is not sensed during that period, the system generates a stimulating pulse and, using T wave parameters in the ventricular filter, tests to verify capture.

Abstract: A cardiac pacer has separate digital filter circuits for sensing atrial and ventricular activity. Parameter data stored in memory is used by the digital filters for identifying the various components of cardiac activity, such as the P, R and T waves, as well as for identifying Premature Ventricular Contractions (PVC). A Ventricular Rate Time Out period is established from the last natural beat or stimulating pulse; and if a P wave or natural R wave is not sensed during that period, the system generates a stimulating pulse and, using T wave parameters in the ventricular filter, tests to verify capture. Loss of capture increases stimulating pulse width and amplitude to regain capture. If a P wave is sensed before the Rate Time Out period ends, the system establishes a predetermined P-R interval period to override the Ventricular Rate Time Out period in which the ventricular filter is set to detect a natural R wave in an effort to synchronize the ventricle with the atrium.