Abstract: In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving an indication of a loss of redundancy with respect to a pair of mirrored memory regions of a partially redundant memory system, determining new mirrored memory regions, and dynamically migrating information stored in the original mirrored memory regions to the new mirrored memory regions. Other embodiments are described and claimed.

Abstract: A method includes determining an amount of memory space in a memory device available for memory mirroring. The method further includes presenting the available memory space to an operating system. The method further includes selecting at least a portion of the amount of memory space to be used for memory mirroring with the operating system. The method further includes adding a non-selected portion of the available memory to memory space available to the operating system during operation. An associated system and machine readable medium are also disclosed.

Abstract: In some embodiments, the invention involves a system and method to continuously log correctable errors without rebooting by changing the granularity of the error detection and logging mechanism. A mask register is used to identify which errors are to be logged. Each bit of the mask register may represent a different memory component of the system. Logging of the memory component is determined by the value of the bit in the mask. The masking enables granularity of error logging to the channel and/or dual in-line memory module (DIMM) level. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract: One embodiment of the invention includes a memory RAS mode whereby a multi-channel memory controller utilizes both memory mirroring and memory sparing to form more complete memory redundancy loss protection.

Abstract: Methods and apparatus dynamically reconfigure storage or channel capacities in a memory system. A fully-buffered dual in-line memory module (DIMM) is configured for a particular storage capacity and a particular channel capacity. An error may be detected at a memory address in some portion of the DIMM. To resolve the problem, the storage capacity or the channel capacity may be reduced and the DIMM may be dynamically reconfigured according to the reduced capacity. For one embodiment the DIMM may be reconfigured by mapping the portion of the DIMM containing the error as unavailable and taking that portion off-line without taking the entire DIMM off-line. For another embodiment the DIMM may be reconfigured by throttling the DIMM at a reduced frequency. The portion of the DIMM containing the error may be retested at the reduced frequency. If no errors are detected, the DIMM may be made available at the reduced frequency.

Abstract: A virtual machine monitor (VMM) in a data processing system handles errors involving virtual machines (VMs) in the processing system. For instance, an error manager in the VMM may detect an uncorrectable error in involving a component associated with a first VM in the processing system. In response to detection of that error, the error manager may terminate the first VM, while allowing a second VM in the processing system to continue operating. In one embodiment, the error manager automatically determines which VM is affected by the uncorrectable error, in response to detecting the uncorrectable error. The error manager may also automatically spawn a new VM to replace the first VM, if the processing system has sufficient resources to support the new VM. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for allocating a fail-over memory region, determining if multiple processors have reached a rendezvous state, and verifying a memory failure in a system software memory region associated with a non-rendezvousing processor and sending a message to the non-rendezvousing processor to update a range register to the fail-over memory region. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for executing a first code portion of a pre-boot environment from a first non-volatile memory, authenticating a trusted hypervisor in the first non-volatile memory using the first code portion, executing the trusted hypervisor if the trusted hypervisor is authenticated, and authenticating a basic input/output system (BIOS) present in a second non-volatile memory with the trusted hypervisor and transferring control from the trusted hypervisor to the BIOS if the BIOS is authenticated. Other embodiments are described and claimed.

Abstract: In some embodiments, the invention involves a system and method to provide maximal boot-time parallelism for future multi-core, multi-node, and many-core systems. In an embodiment, the security (SEC), pre-EFI initialization (PEI), and then driver execution environment (DXE) phases are executed in parallel on multiple compute nodes (sockets) of a platform. Once the SEC/PEI/DXE phases are executed on all compute nodes having a processor, the boot device select (BDS) phase completes the boot by merging or partitioning the compute nodes based on a platform policy. Partitioned compute nodes each run their own instance of EFI. A common memory map may be generated prior to operating system (OS) launch when compute nodes are to be merged. Other embodiments are described and claimed.

Abstract: Provided are a method, system, and article of manufacture, wherein instructions stored in an option ROM are copied to the system memory of a computer, wherein the option ROM corresponds to a device that is coupled to the computer. A virtual machine is generated, wherein the virtual machine executes the instructions copied to the system memory to boot the device before any operating system is loaded.

Abstract: A method and apparatus is described herein for fault resilient booting of a platform. Upon booting the platform, any boot routines marked are skipped. A current boot routine to be executed in a boot sequence is registered in nonvolatile memory. An attempt to execute the current boot routine is made. If the attempt is successful, the next boot entry is determined and skipped or executed, based on whether it is marked. However, if the execution fails the current boot routine is marked and, upon subsequent execution of the boot sequence, skipped.

Abstract: Methods and apparatus to facilitate fast restarts in processor systems are disclosed. An example processor restart method disclosed herein includes recording a log of pre-boot initialization actions, and replaying a portion of the log during subsequent processor restarts to shorten pre-boot initialization time. The example processor restart method disclosed herein may further include creating a log index table for easier referral to portions of the log, storing the log and the log index table in non-volatile memory, using the log index table to reorder the replaying of the log, and reordering the replay of the log to initialize the video graphics adapter earlier in a processor restart sequence.

Abstract: Methods and apparatus to manage throttling in computing environments are described herein. One example method may include receiving an indication that a first memory module has reached a temperature and remapping information from the first memory module to a second memory in response to the received indication. Other methods are described.

Abstract: A method includes determining an amount of memory space in a memory device available for memory mirroring. The method further includes presenting the available memory space to an operating system. The method further includes selecting at least a portion of the amount of memory space to be used for memory mirroring with the operating system. The method further includes adding a non-selected portion of the available memory to memory space available to the operating system during operation. An associated system and machine readable medium are also disclosed.

Abstract: One embodiment of the invention includes a memory RAS mode whereby a multi-channel memory controller utilizes both memory mirroring and memory sparing to form more complete memory redundancy loss protection.

Abstract: A virtual machine monitor (VMM) in a data processing system handles errors involving virtual machines (VMs) in the processing system. For instance, an error manager in the VMM may detect an uncorrectable error in involving a component associated with a first VM in the processing system. In response to detection of that error, the error manager may terminate the first VM, while allowing a second VM in the processing system to continue operating. In one embodiment, the error manager automatically determines which VM is affected by the uncorrectable error, in response to detecting the uncorrectable error. The error manager may also automatically spawn a new VM to replace the first VM, if the processing system has sufficient resources to support the new VM. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for creating a virtual machine (VM) in a server platform having a baseboard management controller (BMC) and enabling the VM to virtualize the BMC, receiving a request in the VM for performing a BMC function in the VM, initiating a communication from the VM to the BMC, and trapping the communication in management software of the server platform and routing the communication to a predetermined port of the BMC. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for executing a first code portion of a pre-boot environment from a first non-volatile memory, authenticating a trusted hypervisor in the first non-volatile memory using the first code portion, executing the trusted hypervisor if the trusted hypervisor is authenticated, and authenticating a basic input/output system (BIOS) present in a second non-volatile memory with the trusted hypervisor and transferring control from the trusted hypervisor to the BIOS if the BIOS is authenticated. Other embodiments are described and claimed.