Abstract: An embodiment includes a secure and stable method for sending information across a compute continuum. For example, the method may include executing an application (e.g., video player) on a first node (e.g., tablet) with a desire to perform “context migration” to a second node (e.g., desktop). This may allow a user to watch a movie on the tablet, stop watching the movie, and then resume watching the movie from the desktop. To do so in a secure and stable manner, the first node may request security and performance credentials from the second node. If both credential sets satisfy thresholds, the first node may transfer content (e.g., encrypted copy of a movie) and state information (e.g., placeholder indicating where the movie was when context transfer began). The second node may then allow the user to resume his or her movie watching from the desktop. Other embodiments are described herein.

Abstract: Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract: An apparatus includes a memory that is accessible by an operating system; and a basic input/output system (BIOS) handler. The BIOS handler, in response to detected malicious software activity, stores data in the memory to report the activity to the operating system.

Abstract: Methods and apparatus relating to pre-OS (pre Operating System) image rewriting to provide cross-architecture support, security introspection, and/or performance optimization are described. In an embodiment, logic rewrites a non-native firmware interface driver into a native firmware interface driver in response to a determination that sufficient space is available in an integrity cache storage device to store the native firmware interface driver. The logic rewrites the non-native firmware interface driver into the native firmware interface driver by performing one or more of its operations during operating system runtime. Other embodiments are also claimed and described.

Abstract: Embodiments of multinode hubs for trust operations are disclosed herein. In some embodiments, a multinode hub may include a plurality of memory regions, a trapping module, and a trusted platform module (TPM) component. Each memory region may be associated with and receive trust operation data from a coherent computing node. The trapping module may generate trap notifications in response to accesses to the plurality of memory regions by the associated coherent computing nodes. The trap notifications may indicate which of the plurality of memory locations has been accessed, and the TPM component may process the trust operation data in a memory region indicated by a trap notification. Other embodiments may be disclosed and/or claimed.

Abstract: Method and apparatus for dynamic Node healing in a Multi-Node environment. A multi-node platform controller hub (MN-PCH) is configured to support multiple nodes through use of dedicated interfaces and components and shared capabilities. Interfaces and components may be configured to be used by respective nodes, or may be configured to support enhanced resiliency as redundant primary and spare interfaces and components. In response to detecting a failing or failing primary interface or component, the MN-PCH automatically performs failover operations to replace the primary with the spare. Moreover, the failover operation is transparent to the operating systems running on the platform's nodes.

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.

Abstract: In one embodiment a controller comprises logic to determine whether an electronic device is operating in a low power state and in response to a determination that the electronic device is operating in a low power state, implement a memory state management routine which reduces power to at least a section of volatile memory in the memory system. Other embodiments may be described.

Abstract: Embodiments of multinode hubs for trust operations are disclosed herein. In some embodiments, a multinode hub may include a plurality of memory regions, a trapping module, and a trusted platform module (TPM) component. Each memory region may be associated with and receive trust operation data from a coherent computing node. The trapping module may generate trap notifications in response to accesses to the plurality of memory regions by the associated coherent computing nodes. The trap notifications may indicate which of the plurality of memory locations has been accessed, and the TPM component may process the trust operation data in a memory region indicated by a trap notification. Other embodiments may be disclosed and/or claimed.

Abstract: Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.

Abstract: In accordance with some embodiments, a single trusted platform module per platform may be used to handle conventional trusted platform tasks as well as those that would arise prior to the existence of a primary trusted platform module in conventional systems. Thus one single trusted platform module may handle measurements of all aspects of the platform including the baseboard management controller. In some embodiments, a management engine image is validated using a read only memory embedded in a chipset such as a platform controller hub, as the root of trust. Before the baseboard management controller (BMC) is allowed to boot, it must validate the integrity of its flash memory. But the BMC image may be stored in a memory coupled to a platform controller hub (PCH) in a way that it can be validated by the PCH.

Abstract: Some aspects include beginning a power on self test (POST) by a BIOS for a computer system; enumerating the computer system by the BIOS; providing, based on the enumeration of the computer system by the BIOS, at least one configuration setting of the computer system to a management engine (ME) of the computer system; and applying a lock to the at least one configuration setting by the ME to manage a change to the at least one configuration setting, all prior to an ending of the POST.

Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.

Abstract: Systems and methods may provide for detecting a pending write operation directed to a target memory region and determining whether the target memory region satisfies a degradation condition in response to the pending write operation. Additionally, the target memory region may be automatically reconfigured as a cold storage region if the target memory region satisfies the degradation condition. In one example, determining whether the target memory region satisfies the degradation condition includes updating the number of write operations directed to the target memory region based on the pending write operation and comparing the number of write operations to an offset value, wherein the degradation condition is satisfied if the number of write operations exceeds the offset value.

Abstract: An embodiment includes a secure and stable method for sending information across a compute continuum. For example, the method may include executing an application (e.g., video player) on a first node (e.g., tablet) with a desire to perform “context migration” to a second node (e.g., desktop). This may allow a user to watch a movie on the tablet, stop watching the movie, and then resume watching the movie from the desktop. To do so in a secure and stable manner, the first node may request security and performance credentials from the second node. If both credential sets satisfy thresholds, the first node may transfer content (e.g., encrypted copy of a movie) and state information (e.g., placeholder indicating where the movie was when context transfer began). The second node may then allow the user to resume his or her movie watching from the desktop. Other embodiments are described herein.

Abstract: Techniques and mechanisms for providing access to a storage device of a computer platform. In an embodiment, an agent executing on the platform may be registered for access to the storage device, the agent being allocated a memory space by a host operating system of the platform. Registration of the agent may result in a location in the allocated memory space being mapped to a location in the storage device. In another embodiment, the agent may write to the location in the allocated memory space to request access to the storage device, wherein the request is independent of any system call to the host OS which describes the requested access.

Abstract: Method and apparatus for dynamic Node healing in a Multi-Node environment. A multi-node platform controller hub (MN-PCH) is configured to support multiple nodes through use of dedicated interfaces and components and shared capabilities. Interfaces and components may be configured to be used by respective nodes, or may be configured to support enhanced resiliency as redundant primary and spare interfaces and components. In response to detecting a failing or failing primary interface or component, the MN-PCH automatically performs failover operations to replace the primary with the spare. Moreover, the failover operation is transparent to the operating systems running on the platform's nodes.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for a Unified Extensible Firmware Interface (UEFI) with durable storage to provide memory write persistence, for example, in the event of power loss. The system may include a processor to host the firmware interface which may be configured to control access to system variables in a protected region of a volatile memory. The system may also include a power management circuit to provide power to the processor and further to provide a power loss indicator to the firmware interface. The system may also include a reserve energy storage module to provide power to the processor in response to the power loss indicator. The firmware interface is further configured to copy the system variables from the volatile memory to a non-volatile memory in response to the power loss indicator.