Patents by Inventor Robert C. Taft

Robert C. Taft has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5504363
    Abstract: Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertically stacked region is fully depleted and thus reduces the parasitic capacitance between the semiconductor device and the well region.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: April 2, 1996
    Assignee: Motorola Inc.
    Inventors: Robert C. Taft, James D. Hayden
  • Patent number: 5441914
    Abstract: In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and the overlying patterned silicon nitride anti-reflective layer (26).
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: August 15, 1995
    Assignee: Motorola Inc.
    Inventors: Robert C. Taft, Craig D. Gunderson, Arkalgud R. Sitaram
  • Patent number: 5300454
    Abstract: A method for forming a first doped region (24) and a second doped region (26) within a substrate (12). A masking layer (14) overlies the substrate (12). A first region (20) of the masking layer (14) is etched to form a first plurality of openings. A second region (22) of the masking layer (14) is etched to form a single opening or a second plurality of openings different in geometry from the first plurality of openings. A single ion implant step or an equivalent doping step is used to dope exposed portions of the substrate (12). The geometric differences in the masking layer (14) between region (20) and region (22) results in the formation of the first and second doped regions (24 and 26) wherein the first and second doped regions (24 and 26) vary in doping uniformity, doping concentration, and doping junction depth.
    Type: Grant
    Filed: November 24, 1992
    Date of Patent: April 5, 1994
    Assignee: Motorola, Inc.
    Inventors: Robert C. Taft, Ravi Subrahmanyan
  • Patent number: 4825269
    Abstract: A bipolar transistor in which the base region includes a heterostructure and a doped layer of semiconductor material with the heterostructure functioning as a two-dimensional hole gas. The doped layer is sufficiently thin to prevent occurrence of a charge-neutral region of holes. In operation the transistor can switch quickly since minority charge storage in the base region does not present a problem. The device lends itself to downscaling in size in a VLSI circuit.
    Type: Grant
    Filed: March 4, 1988
    Date of Patent: April 25, 1989
    Assignee: Stanford University
    Inventors: James D. Plummer, Robert C. Taft