Abstract: A coil structure for a filter device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil. A portion of the second coil is oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A portion of the third coil is oriented interiorly of the second coil.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

Abstract: A differently-tuned voltage controlled oscillator (VCO) and its application in a multi-band VCO tuner are disclosed. In one aspect of the invention, the VCO comprises a plurality of serially connected inductive elements each including inductively coupled inductor elements, a varactor element connected in parallel with the serially connected first inductor elements and means to apply a first and second tuning voltage to elements of the varactor element. In a second aspect, the VCO further comprises a second varactor element connected in parallel with the inductive elements, and means to apply the second tuning voltage elements of the second varactor element.

Abstract: A differently-tuned voltage controlled oscillator (VCO) and its application in a multi-band VCO tuner are disclosed. In one aspect of the invention, the VCO comprises a plurality of serially connected inductive elements each including inductively coupled inductor elements, a varactor element connected in parallel with the serially connected first inductor elements and means to apply a first and second tuning voltage to elements of the varactor element. In a second aspect, the VCO further comprises a second varactor element connected in parallel with the inductive elements, and means to apply the second tuning voltage elements of the second varactor element.

Abstract: The specification describes a high density I/O IC package in which the IC chip is bonded to a silicon intermediate interconnection substrate (IIS), and the IIS is wire bonded to a printed wiring board. This marriage of wire bond technology with high density I/O IC chips results in a low cost, high reliability, state of the art IC package.

Abstract: The specification describes method for improving the edge acuity of conductive metal strips formed by thick film paste techniques. The advantages of the bulk properties of strips formed using thick film technology are realized while the drawback of poor edge definition is overcome using a thin film trim strip at the edge of the conductive strip.

Abstract: The specification describes a recessed chip IC package in which the IC chip is bonded to a silicon translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The thermal mismatch between the silicon translator and conventional printed wiring board materials is addressed by using an interposer which is essentially a ball grid array of plated-through holes that transfers the interconnect pattern from the translator to the printed wiring board. The interposer may have a composition with a coefficient of thermal expansion (CTE) that lies between the CTE of silicon and the CTE of the board material. It may also be provided with holes or slots for additional stress relief.

Abstract: The specification describes a recessed chip IC package in which the IC chip is bonded to a translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The translator also has a large area outboard of the IC chip area to allow fan out from high pin count chips to large pitch interconnection sites for interconnection to the next board level.

Abstract: The specification describes a recessed chip IC package in which the cavity in the printed wiring board into which the IC chip is recessed is used as a through hole interconnection, thus increasing the interconnection density. If the through cavity interconnections are used as power and ground the signal I/O pads and the signal runners are effectively isolated.

Abstract: A balanced/unbalanced (balun) transformer has at least one pair of stacked coupled spiral lines. The spiral lines are formed on different levels of the device with the upper spiral line nested between the lower spiral line. This structure allows the width W and spacing S of the lines to be independently varied. Analysis of devices made with this configuration shows an optimum ratio of W to W+S of from 0.4 to 0.6.

Abstract: The specification describes interconnection layouts for chip-on-chip packages using solder bump interchip connections as vias between a single level metal interconnection pattern on the lower support IC chip and another single level interconnection pattern on the upper IC chip. This arrangement allows for the formation of air isolated crossovers of features on either chip.

Abstract: A silicon-on-silicon dual MCM apparatus comprising a printed circuit board having a voltage isolation boundary contained therein supporting a pair of multi-chip modules on either side of the voltage isolation boundary. The MCMs safely convey signals across the isolation boundary via discrete optical coupling means or the like. The optical coupling means allow safe and efficient conveyance of signals across the voltage isolation boundary enabling a designer to group high voltage components on one side of the boundary and low voltage components on the other side of the boundary. This obviates to a degree the need for multi-layered PCBs. A relatively large number of passive components (resistors and capacitors) are integrated into a silicon substrate with flip-chip analog integrated circuits (ICs). Operational characteristics of the controller are verified after integration and are compared to the discrete version.

Abstract: The present invention is predicated upon the fact that an emission trace from a plasma glow used in fabricating integrated circuits contains information about phenoma which cause variations in the fabrication process such as age of the plasma reactor, densities of the wafers exposed to the plasma, chemistry of the plasma, and concentration of the remaining material. In accordance with the present invention, a method for using neural networks to determine plasma etch end-point times in an integrated circuit fabrication process is disclosed. The end-point time is based on in-situ monitoring of the optical emission trace. The back-propagation method is used to train the network. More generally, a neural network can be used to regulate control variables and materials in a manufacturing process to yield an output product with desired quality attributes. An identified process signature which reflects the relation between the quality attribute and the process may be used to train the neural network.

Abstract: Insulated gate field effect transistor charge regenerator amplifiers respectively cross-couple the output regions of a pair of two-phase CCD structures with the input regions of those structures. Each amplifier senses the level of binary data charge packets from the output region of one of the shift register structures and in response thereto applies a regenerated and inverted binary data charge packet to the input region of the other shift register structure. One of the amplifiers includes logic gating for inputting and outputting data into and from the shift register structure.A charge regenerator for a two-phase CCD structure comprising first and second shift registers. The charge regenerator comprises a source follower amplifier including a driver transistor, a load transistor and a positive feedback transistor connected between the gate and source of the driver transistor.

Abstract: Semiconductor memory cells include gate conductor-insulator-semiconductor regions having storage and transfer portions in which the threshold voltage and surface potential-gate conductor voltage characteristics differ as between the storage and transfer portions. This may be achieved by employing relatively thick and relatively thin insulator areas at the storage and transfer portions, or vice versa, with a surface charge accumulation layer at the semiconductor region insulator interface. In a different form of cell structure, the insulator is a uniform thickness layer overlying the storage and transfer portions one of which includes a doped semiconductor region of the same conductivity type as, but higher dopant concentration than, the remainder of the semiconductor region.

Abstract: A continuous gate electrode overlies the channel of the CCD and is connected to a uniphase clock pulse source for operation of the CCD. Pairs of gate conductor-insulator-semiconductor regions are defined along the channel. In each pair of regions the surface potential-gate voltage characteristic of one region intersects that of the other region, such that in the OFF condition of a clock pulse the potential well at one region of each pair is deeper than that of the other region; in the ON condition of a clock pulse, this situation is reversed. In this manner, charge packets are propagated along the channel and unidirectionality is achieved by locally implanted potential wells or potential barriers in each of the aforesaid regions.