Abstract: Systems and methods of the present disclosure include at least one building component detection sensor device configured to be deployed within (or proximate to) a building comprised of a plurality of building components. The at least one building component detection sensor device is configured to detect data relating to at least one building component of the plurality of building components. In addition, a building component property determination system includes a processor configured to execute instructions stored in memory to determine one or more properties of the at least one building component based at least in part on the data detected by the at least one building component detection sensor device.

Abstract: The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.

Abstract: A virtual electronic fuse apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back to a virtual blown state.

Abstract: A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets. A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.

Abstract: The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.

Abstract: A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets. A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.

Abstract: A virtual electronic fuse (VEF) apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back again to a virtual blown state. The fuse apparatus includes multiple VEFs, each VEF exhibiting a respective address. The fuse apparatus also includes an address pool including multiple address pool locations. A fuse programmer stores an address of one of the VEFs in one or more address pool locations to indicate one or more state changes for a particular VEF. The fuse programmer may also store different VEF addresses in different address pool locations to indicate state changes for different VEFs.

Abstract: A virtual electronic fuse (VEF) apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back again to a virtual blown state. The fuse apparatus includes multiple VEFs, each VEF exhibiting a respective address. The fuse apparatus also includes an address pool including multiple address pool locations. A fuse programmer stores an address of one of the VEFs in one or more address pool locations to indicate one or more state changes for a particular VEF. The fuse programmer may also store different VEF addresses in different address pool locations to indicate state changes for different VEFs.

Abstract: A virtual electronic fuse apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back to a virtual blown state.

Abstract: The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. The processor is coupled to the controller and configured to generate self-identify control signals and to transmit the self-identify control signals to the controller.

Abstract: A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.

Abstract: An apparatus, a method, and a computer program product are provided for identifying signals in analogue electrical systems. The ID select signals that control the timing of this signal identification circuit comprise sequential numbers that count up and identify a corresponding signal. The signals to be identified are located on a group of input/output (I/O) pins. One multiplexer (first) selects a specific I/O pin in response to the ID select signals. An isolated voltage source is connected to this multiplexer and provides the selected signal to another multiplexer (second). The second multiplexer switches from this isolated voltage source to ground potential in response to the ID select signals. The isolated voltage source floats at the DC level of the selected I/O driver pin. Therefore, by connecting to the selected signal's I/O pin and the output of the second multiplexer, the selected signal can be identified and then probed.

Abstract: A method and apparatus are provided for protecting electronic fuse (eFuse) information. A current balancing circuit is provided that maintains a constant current demand on the eFuse voltage supply that is sufficient to blow an eFuse. Normally the constant current is applied to a semiconductor core. When an eFuse is being blown, the constant current is diverted away from the core to the eFuse and as the eFuse blows, the constant current is again dumped to the semiconductor core. Thus, a change in current due to the transient of the eFuse being blown is not detectable and the information that an eFuse has been blown is kept secure.

Abstract: In one aspect, a method for performing clocked operations in a device includes performing, in a device, first and second operations responsive to a clock having a primary frequency f. The device is capable of performing the operations within X and Y cycles of the clock, respectively. X cycles of the clock correspond to a time interval T1 with the clock operating at the frequency f, and, accordingly, the device is capable of performing X/Y instances of the second operation within time interval T1 with the clock operating at the frequency f. During the time interval T1 at least one extra cycle of the clock is generated to reduce performance time for the first operation. An affect of the at least one extra cycle is masked with respect to the second operation, so that instances of the second operation during the interval T1 remain no greater in number than X/Y.

Abstract: In one form of the invention, an apparatus for visually displaying a non-volatile message includes an integrated circuit having first circuitry. The apparatus also includes a package for the integrated circuit and a display affixed to the integrated circuit package. The first circuitry is coupled to the display and operable to be coupled to an electronic device by pins of the integrated circuit package and to write a non-volatile, visual image via the display responsive to receiving a message from the electronic device.

Abstract: In one aspect of the invention, a method for testing includes interposing a tester between first and second logic. The first logic and second logic have respective first and second output drivers. The tester operates in test cycles to detect dynamic contention responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during an immediately succeeding one of the test cycles. Static contention is detected responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during the same one of the test cycles.

Abstract: In one form of the invention, an apparatus has a first switch operable in an error injection state for interrupting a transfer of first data from a memory device to a test system, and in a normal state for permitting unimpeded data transfer. The apparatus has a second switch operable in an error injection state for sending second data to the test system instead of corresponding bits of the first data. Logic circuitry of the apparatus reads the first data and controls an error injection sequence that includes switching the first and second switches from their respective normal states to their respective error injection states responsive to receiving the command. The apparatus determines whether at least one of the corresponding data bits of the first and second data have disparate logic states independently of switching the first and second switches back to their respective normal states.

Abstract: A multiple fan monitoring circuit for use with a plurality of fans, wherein each of the fans operates at a different frequency and generates a tach signal indicative of the fan operation, including a number of waveform shaping networks coupled to a corresponding one of the fans and utilized to waveshape a tach signal generated by its corresponding fan. The multiple fan monitoring circuit also includes a frequency processing circuit, coupled to the waveform shaping networks, that receives the waveshaped tach signals at a single sense node. The frequency processing circuit includes a summing circuit, coupled to the single sense node, that combines the waveshaped tach signals into a single combined signal, and a frequency discriminator, coupled to the summing circuit, that separates the single combined signal into multiple components, wherein each of the multiple components corresponds to a particular fan.

Abstract: In one form of the invention, an apparatus for visually displaying a non-volatile message includes an integrated circuit having first circuitry. The apparatus also includes a package for the integrated circuit and a display affixed to the integrated circuit package. The first circuitry is coupled to the display and operable to be coupled to an electronic device by pins of the integrated circuit package and to write a non-volatile, visual image via the display responsive to receiving a message from the electronic device.

Abstract: A multiple fan sensing circuit for use with a single fan sense input and method of operation thereof. The multiple fan sensing circuit includes a logic circuit, coupled to the fan sense input, that combines feedback signals from a first fan and a second fan. The first fan generates a tach signal indicative of the first fan operation and the second fan, e.g., a stuck rotor type fan, generates either an ON or OFF signal indicative of the second fan operation. In a related embodiment, the second fan generates a logic high signal in response to a failure in the second fan. In an advantageous embodiment, the logic circuit is a connector and a logic low level in the combined operational signal indicates a failed fan.