Abstract: In one aspect, a method for performing clocked operations in a device includes performing, in a device, first and second operations responsive to a clock having a primary frequency f. The device is capable of performing the operations within X and Y cycles of the clock, respectively. X cycles of the clock correspond to a time interval T1 with the clock operating at the frequency f, and, accordingly, the device is capable of performing X/Y instances of the second operation within time interval T1 with the clock operating at the frequency f. During the time interval T1 at least one extra cycle of the clock is generated to reduce performance time for the first operation. An affect of the at least one extra cycle is masked with respect to the second operation, so that instances of the second operation during the interval T1 remain no greater in number than X/Y.

Abstract: In one aspect of the invention, a method for testing includes interposing a tester between first and second logic. The first logic and second logic have respective first and second output drivers. The tester operates in test cycles to detect dynamic contention responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during an immediately succeeding one of the test cycles. Static contention is detected responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during the same one of the test cycles.

Abstract: A method in a data processing system for identifying a circuit. In a preferred embodiment, a set of bits, with a defined chain length, are shifted into the circuit one bit at a time. The bits shifted out from the circuit are compared to the bits, from the set of bits, shifted into the circuit to determine if the circuit corresponds to a first type circuit. The comparing step is accomplished before all bits in the set of bits have been shifted into the circuit. If the circuit is not a first type circuit corresponding to the set of bits shifted into the circuit, then the shifting of bits into the circuit is discontinued and the process is repeated with a second set of bits corresponding to a second circuit type until the circuit type has been identified.

Abstract: An apparatus and method for memory bus tuning are implemented. A plurality of drivers having a plurality of selectable drive levels are coupled to a memory bus. The memory bus is connected to a memory device which may have a variable amount of memory, which may be in the form of dual-in-line memory modules (DIMM). A drive level is selected in response to a determination of the amount of memory included in the memory device. A register operable for receiving a data value corresponding to the amount of memory is coupled to the drivers, the drive level being selected thereby.

Abstract: A multiple fan monitoring circuit for use with a plurality of fans, wherein each of the fans operates at a different frequency and generates a tach signal indicative of the fan operation. The multiple fan monitoring circuit includes a number of waveform shaping networks, wherein each of the waveform shaping networks is coupled to a corresponding one of the fans. Each of the waveform shaping circuit is utilized to waveshape a tach signal generated by its corresponding fan. The multiple fan monitoring circuit also includes a frequency processing circuit, coupled to the waveform shaping networks, that receives the waveshaped tach signals at a single sense node. In a related embodiment, the frequency processing circuit includes a summing circuit, coupled to the single sense node, that combines the waveshaped tach signals into a single combined signal.

Abstract: A multiple fan sensing circuit for use with a single fan sense input and method of operation thereof. The multiple fan sensing circuit includes a logic circuit, coupled to the fan sense input, that combines feedback signals from a first fan and a second fan. The first fan generates a tach signal indicative of the first fan operation and the second fan, e.g., a stuck rotor type fan, generates either an ON or OFF signal indicative of the second fan operation. In a related embodiment, the second fan generates a logic high signal in response to a failure in the second fan. In an advantageous embodiment, the logic circuit is a connector and a logic low level in the combined operational signal indicates a failed fan. In another aspect of the present invention, an upgradeable fan circuit for use with a cooling system having a first fan that provides a tach feedback signal through a feedback connector is disclosed.

Abstract: An ECC verification circuit including a first biasing circuit that is configured to output a predetermined logical signal. The verification circuit further includes a switch connected between the first biasing circuit and a first data bit line of a memory data bus of a computer system. The memory data bus includes a plurality of data bit lines and a plurality of check bit lines and the computer system includes error correction circuitry that is coupled to the memory data bus. The verification circuit is configured to activate the switch during a verification cycle of the computer system. In this manner, the predetermined logical signal is applied to the first data bit line during the verification cycle. The verification circuit is designed to apply a test state to the data bit lines and check bits lines of the memory data bus.

Abstract: A method of passing transmissions through an error-correction code (ECC) block in a communications path of a computer system. The communications path interconnects a first component of the computer system (such as a random-access memory (RAM) device) and a second component of the computer system (such as a central processing unit (CPU)) using a first granularity, and a third component (such as a read-only memory (ROM) device) is further connected to the communications path such that the third component may transmit data to the second component using a second granularity which is smaller than the first granularity. The data from the third component passes through the ECC block by merging data from the third component with predefined data to present a merged data word to the ECC circuit, wherein the merged data word has the first granularity. The first granularity may be, e.g., 72 bits, while the second granularity is 8 bits.

Abstract: A bus termination impedance verification circuit. The verification circuit includes a sense circuit comprised of a sense input node and a sense output node. A sense node of the sense circuit is connected to a signal conductor of a bus to detect the termination impedance of the bus. The voltage of the sense output node is indicative of the termination impedance of the bus when the sense circuit input node is activated. The comparator circuit includes a comparator input node and a comparator output node. The comparator input node is connected to the sense circuit output node. The comparator circuit is configured such that the comparator output node is indicative of whether the voltage of the comparator input node is within a specified voltage range. The voltage of the signal conductor, as detected by the sense circuit, will be a function of the impedance of the termination circuits connected to the bus.

Abstract: A method and implementing system is provided which includes a switching device as part of a circuit board transmission line or trace serially connecting a plurality of device terminal sockets to a common node. When device terminals are left unconnected, corresponding segments of the connecting transmission line on the circuit board are disconnected to provide transmission line segments corresponding to the number of devices actually used. As a result, signal transition time for signals at the common node is optimized in accordance with the number of devices actually used.

Abstract: A method and apparatus for driving a battery-backed up clock while a computer system is powered-down. The present invention uses an auxiliary power supply, VAUX, to power a microprocessor bus oscillator. The microprocessor bus oscillator is typically a high frequency, highly accurate oscillator. The microprocessor bus oscillator continues to run while the computer system is powered down, but is connected to a wall outlet. Thus, it can be used to synthesize an accurate time base to drive a battery-backed up clock input. A microcontroller, PAL, or other such circuit can be used to convert the high frequency signal from the microprocessor bus oscillator to a frequency suitable for the battery-backed up clock. Thus, a single oscillator is used to keep time for normal operations. Only when the system is moved, or when main power fails, is a battery backed-up crystal oscillator used to keep time. This minimizes the occurrence of timing errors, due to the system being turned off and back on.

Abstract: A connector on a printed circuit board of a computer system is reused to reduce a number of connectors utilized on a motherboard of a computer system. By recognizing that some signals are common between a programming application performed during a manufacturing process and a second application performed while the computer system is a normal customer operation, the connector may be used to provide data values during both the manufacturing process and normal customer operation. Stated another way, data signals used to drive programmed data during the manufacturing process may be re-used to provide serial data to an input/output device during normal customer operation.

Abstract: A method and implementing system are provided for determining and retaining an identification number relevant to an electronic system component and/or component configuration. In an exemplary embodiment, existing pull-up resistors within a computer system are connected in a manner to enable associated circuitry to determine a pre-assigned identification number for the computer system. The identification number is stored in an identification number register and accessible for providing the identification number in response to a requests from other devices within the system.

Abstract: A computer system includes a memory subsystem which has DIMM slots capable of receiving both DRAM and SDRAM memory module devices. A memory device detection methodology detects the presence of installed memory modules in the memory module slots, and signal levels on predetermined pins of the installed memory modules are processed to identify the specific type of memory module installed. The mode of an associated memory controller is set according to the type of module detected to be present, and the characteristics for the memory module are read.

Abstract: A process and implementing computer system in which a power-on self-test (POST) routine initially clears 203 a mask register 111 which is effective to mask or block data from being written to addresses in a synchronous DRAM or SDRAM 107. After disabling interrupts and caches, the tested SDRAM memory 107 is cleared to all "0"s. Sequential data byte lanes are tested by writing bits in a predetermined pattern to inject errors at predetermined bytes in SDRAM, setting selected mask register bits and then writing all "0"s to the predetermined addresses. The tested memory locations are read and compared with the predetermined pattern for errors. Detected errors are noted by recordation and the memory locations are cleared as the method recycles until all of the data byte lanes have been tested and the results recorded.

Abstract: An error generator for use with a memory device, such as dynamic random-access memory (DRAM) which is connected to an error detection or correction device, such as a memory controller using error-correcting code. The memory error generator uses a clock signal provided by the computer system, determines when the computer system first attempts to read from a data stream after synchronization, and thereafter introduces the error in at least one bit of the data stream by complementing the bit. The error generator can be provided with a switch such that synchronization is performed in response to activation of the switch. The error generator preferably is constructed using an inexpensive device, such as a programmable array logic (PAL) circuit. Use of a PAL allows the bit complementing to occur quickly enough to meet timing requirements of the memory controller. The PAL and switch can be mounted on an interposer which is removably connected to the memory array and the memory controller.

Abstract: A method and apparatus for generating a divisor having a variable value for real time calculations. A microprocessor's time base register is used to generate the divisor. All interrupts and refreshes are disabled on the microprocessor before calculating the divisor. The microprocessor's time base register is cleared and allowed to count the number of clock ticks in a one second interval. The time base register is read and the value used as a divisor for real time calculations.