Patents by Inventor Robert D. Edwards
Robert D. Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240124288Abstract: A portable, self-contained beverage apparatus includes a container assembly having a known storage capacity for storing a consumable liquid, and a dispensing assembly disposed within the container assembly that dispenses variable, non-zero quantities of additives into the consumable liquid. The dispensing assembly includes multiple apertures structured and arranged to retain vessels containing the additives to be dispensed into the consumable liquid. The beverage apparatus also includes a level sensor disposed within the container assembly that determines a consumable liquid level of the consumable liquid stored in the container assembly. In certain embodiments, one or more positive displacement pumping mechanisms are configured to pump additive liquid from additive containers into a beverage chamber.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Applicant: Cirkul, Inc.Inventors: Mark Lyons, Jonathon Perrelli, Robert Lawson-Shanks, Abraham Maclean, Connor Bacon, James Christopher Small, Jesse John Horne, Simon Lewis Bilton, Matthew James Edwards, Andrew Gordon Wallace, Maxim D. Wheatley, David J. Wheatley, Todd Metlen
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Patent number: 9702930Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: GrantFiled: April 5, 2016Date of Patent: July 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 9673089Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.Type: GrantFiled: October 31, 2014Date of Patent: June 6, 2017Assignee: AURIGA INNOVATIONS, INCInventors: Griselda Bonilla, Kaushik Chanda, Robert D. Edwards, Ronald G. Filippi, Andrew H. Simon, Ping-Chuan Wang
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Publication number: 20160216321Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: ApplicationFiled: April 5, 2016Publication date: July 28, 2016Inventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 9354252Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: GrantFiled: December 4, 2014Date of Patent: May 31, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 9059111Abstract: A semiconductor structure, method of manufacturing the same and design structure thereof are provided. The semiconductor structure includes a substrate including a semiconductor layer and a plurality of TSVs embedded therein. At least one TSV has a TSV tip extending from a backside surface of the substrate. The semiconductor structure further includes a multilayer metal contact structure positioned on the backside surface of the substrate. The multilayer metal contact structure includes at least a conductive layer covering the backside surface of the substrate and covering protruding surfaces of the TSV tip. The conductive layer has a non-planar first surface and a substantially planar second surface opposite of the first surface.Type: GrantFiled: April 11, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Robert D. Edwards, Jeffrey P. Gambino, Charles F. Musante, Ping-Chuan Wang
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Publication number: 20150145544Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: ApplicationFiled: December 4, 2014Publication date: May 28, 2015Inventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Publication number: 20150056806Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.Type: ApplicationFiled: October 31, 2014Publication date: February 26, 2015Inventors: Griselda Bonilla, Kaushik Chanda, Robert D. Edwards, Ronald G. Filippi, Andrew H. Simon, Ping-Chuan Wang
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Patent number: 8963567Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: GrantFiled: October 31, 2011Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 8912658Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.Type: GrantFiled: October 29, 2010Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Ronald Filippi, Ping-Chuan Wang, Griselda Bonilla, Kaushik Chanda, Robert D. Edwards, Andrew H. Simon
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Publication number: 20140306322Abstract: A semiconductor structure, method of manufacturing the same and design structure thereof are provided. The semiconductor structure includes a substrate including a semiconductor layer and a plurality of TSVs embedded therein. At least one TSV has a TSV tip extending from a backside surface of the substrate. The semiconductor structure further includes a multilayer metal contact structure positioned on the backside surface of the substrate. The multilayer metal contact structure includes at least a conductive layer covering the backside surface of the substrate and covering protruding surfaces of the TSV tip. The conductive layer has a non-planar first surface and a substantially planar second surface opposite of the first surface.Type: ApplicationFiled: April 11, 2013Publication date: October 16, 2014Applicant: International Business Machines CorporationInventors: Robert D. Edwards, Jeffrey P. Gambino, Charles F. Musante, Ping-Chuan Wang
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Publication number: 20130106455Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert D. Edwards, Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Publication number: 20120104610Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.Type: ApplicationFiled: October 29, 2010Publication date: May 3, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald Filippi, Ping-Chuan Wang, Griselda Bonilla, Kaushik Chanda, Robert D. Edwards, Andrew H. Simon
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Patent number: 8053257Abstract: The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for a layer within chips comprising a semiconductor wafer lot. If only one mode is calculated, that is the best calculated mode. If multiple modes can be calculated, a best mode that most accurately represents dielectric breakdown for the semiconductor wafer lot is determined. Premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation from the best calculated mode.Type: GrantFiled: April 2, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Hazara S. Rathore, Paul S. McLaughlin, Robert D. Edwards, Lawrence A. Clevenger, Andrew P. Cowley, Chih-Chao Yang, Conrad A. Barile
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Publication number: 20110260299Abstract: A semiconductor printed circuit board assembly (PCBA) and method for making same for use in electronic packages having a core layer of copper-invar-copper (CIC) with a layer of dielectric substrate placed on the core layer. A second layer of dielectric substrate is placed on the lower surface of the core layer of CIC. The layers are laminated together. Blind vias are laser drilled into the layers of dielectric substrate. The partially completed PCBA is subjected to a reactive ion etch (RIE) plasma as a first step to clean blind vias in the PCBA. After the plasma etch, an acidic etchant liquid solution is used on the blind vias. Pre-plating cleaning of blind vias removes a majority of oxides from the blind vias. Seed copper layers are then applied to the PCBA, followed by a layer of copper plating that can be etched to meet the requirements of the PCBA.Type: ApplicationFiled: April 22, 2010Publication date: October 27, 2011Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.Inventors: Robert D. Edwards, Frank D. Egitto, Luis J. Matienzo, Susan Pitely, Daniel C. Van Hart
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Patent number: 7602265Abstract: The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.Type: GrantFiled: October 20, 2005Date of Patent: October 13, 2009Assignee: International Business Machines CorporationInventors: Hariklia Deligianni, Robert D. Edwards, Thomas J. Fleischman, Robert A. Groves, Charles J. Montrose, Richard P. Volant, Ping-Chuan Wang
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Publication number: 20080174334Abstract: The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.Type: ApplicationFiled: April 2, 2008Publication date: July 24, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kaushik Chanda, Hazara S. Rathore, Paul S. McLaughlin, Robert D. Edwards, Lawrence A. Clevenger, Andrew P. Cowley, Chih-Chao Yang, Conrad A. Barile
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Patent number: 7223476Abstract: Methods for making composite flakes are disclosed. The composite flakes are formed from particles and one or more monomers and/or resins or resin systems. The polymer matrix of the flakes is highly crosslinked and/or high molecular weight. Use of the particles in powder coatings is also disclosed.Type: GrantFiled: June 14, 2004Date of Patent: May 29, 2007Assignee: PPG Industries Ohio, Inc.Inventors: Robert D. Edwards, Jackie L. Kulfan, Calum H. Munro
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Patent number: 7169313Abstract: A method of plating a circuit pattern on a substrate to produce a circuitized substrate (e.g., a printed circuit board) in which a dual step metallurgy application process is used in combination with a dual step photo-resist removal process. Thru-holes are also possible, albeit not required.Type: GrantFiled: May 13, 2005Date of Patent: January 30, 2007Assignee: Endicott Interconnect Technologies, Inc.Inventors: Norman A. Card, Robert D. Edwards, John J. Konrad, Roy H. Magnuson, Timothy L. Wells, Michael Wozniak
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Patent number: 6383617Abstract: Gold is deposited on a copper base defining electrical circuit features disposed on a substrate containing a palladium seeder, by initially treating the substrate with an alkaline cleaner, followed by treating the substrate with sodium persulfate, and subsequently treating the substrate with a diluted sulfuric acid solution. The substrate is rinsed between each one of the treatments, and after the final rinse following treatment with diluted sulfuric acid, the substrate is immersed in a gold deposition solution whereby gold is deposited on the exposed surfaces of the copper circuit features on a substrate. The process embodying the present invention provides a method for depositing gold on high density copper conductor lines or pads, even in areas of the surface in which the conductors are spaced apart 2.0 mil or less, without cleaning or removing the palladium seed from the surface.Type: GrantFiled: April 10, 2000Date of Patent: May 7, 2002Assignee: International Business Machines Corp.Inventors: Gerald L. Ballard, Robert D. Edwards, John G. Gaudiello, Voya R. Markovich