Patents by Inventor Robert D. Hopkins
Robert D. Hopkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922950Abstract: A method according to one embodiment includes receiving audio input by a microphone of an access control device that controls access through a passageway, processing an audio signal associated with the audio input to identify and authenticate a user, determining a command corresponding with the audio signal in response to identification and authentication of the user, and performing at least one action that corresponds with the command.Type: GrantFiled: April 12, 2022Date of Patent: March 5, 2024Assignee: Schlage Lock Company LLCInventors: Daniel Langenberg, Joseph W. Baumgarte, Joshua Long, Brady Plummer, John D. Goodwin, Dakoda Johnson, Benjamin J. Hopkins, Robert Prostko, Robert Martens
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Patent number: 8918752Abstract: A semiconductor die is described. This semiconductor die includes a driver, and a spatial alignment transducer that is electrically coupled to the driver and which is proximate to a surface of the semiconductor die. The driver establishes a spatially varying electric charge distribution in at least one direction in the spatial alignment transducer, thereby facilitating determination of a spatial alignment in more than one direction between the semiconductor die and another semiconductor die. In particular, a spatial alignment sensor proximate to the surface of the other semiconductor die may detect an electrical field (or an associated electrostatic potential) associated with the spatially varying electric charge distribution. This detected electric field may allow the vertical spacing between the surfaces of the semiconductor dies and/or an angular alignment of the semiconductor dies to be determined.Type: GrantFiled: December 14, 2011Date of Patent: December 23, 2014Assignee: Oracle International CorporationInventors: Alex Chow, Robert J. Drost, Ronald Ho, Robert D. Hopkins, Ivan E. Sutherland
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Patent number: 8735184Abstract: A device includes a semiconductor die having a surface, a plurality of proximity connectors proximate to the surface, and a circuit coupled to at least one of the plurality of proximity connectors. The semiconductor die is configured to communicate voltage-mode signals through capacitive coupling using one or more of the plurality of proximity connectors. The circuit also includes a filter with a capacitive-summing junction to equalize the signals.Type: GrantFiled: December 30, 2011Date of Patent: May 27, 2014Assignee: Oracle International CorporationInventors: Ronald Ho, Robert D. Hopkins, William S. Coates, Robert J. Drost
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Patent number: 8482072Abstract: A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.Type: GrantFiled: May 16, 2012Date of Patent: July 9, 2013Inventors: Robert J. Drost, Robert D. Hopkins, Alex Chow
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Publication number: 20130154608Abstract: A semiconductor die is described. This semiconductor die includes a driver, and a spatial alignment transducer that is electrically coupled to the driver and which is proximate to a surface of the semiconductor die. The driver establishes a spatially varying electric charge distribution in at least one direction in the spatial alignment transducer, thereby facilitating determination of a spatial alignment in more than one direction between the semiconductor die and another semiconductor die. In particular, a spatial alignment sensor proximate to the surface of the other semiconductor die may detect an electrical field (or an associated electrostatic potential) associated with the spatially varying electric charge distribution. This detected electric field may allow the vertical spacing between the surfaces of the semiconductor dies and/or an angular alignment of the semiconductor dies to be determined.Type: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Alex Chow, Robert J. Drost, Ronald Ho, Robert D. Hopkins, Ivan E. Sutherland
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Patent number: 8299839Abstract: A capacitively and conductively coupled multiplexer (C3mux) circuit is described. This C3mux circuit includes a set of nonlinear coupling capacitors, such as metal-oxide-semiconductor (MOS) transistors, that can multiplex multiple input signals while minimizing the parasitic capacitance penalty associated with the ‘off’ paths. In particular, the capacitance of a given MOS transistor depends on whether its channel is present or absent. Furthermore, this channel is formed based on whether the gate-to-source and drain voltages for the MOS transistor are greater than the MOS transistor's threshold voltage. Note that the capacitance of the MOS transistors in the C3mux circuit is low for the unselected inputs. Consequently, the parasitic loading and the delay increase slowly as a function of the number of inputs. Moreover, the conductive feedback can be used to maintain a DC level of the input signals.Type: GrantFiled: January 12, 2009Date of Patent: October 30, 2012Assignee: Oracle America, Inc.Inventors: Robert J. Drost, Alex Chow, Robert D. Hopkins
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Publication number: 20120229941Abstract: A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.Type: ApplicationFiled: May 16, 2012Publication date: September 13, 2012Applicant: SUN MICROSYSTEMS, INC.Inventors: Robert J. Drost, Robert D. Hopkins, Alex Chow
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Patent number: 8242811Abstract: Some embodiments of the present invention provide techniques and systems for high-bandwidth on-chip communication. During operation, the system receives an input voltage signal which is to be transmitted over a wire in a chip. The system then generates one or more modified voltage signals from the input voltage signal. Next, the system drives each of the voltage signals (i.e., the input voltage signal and the one or more modified voltage signals) through a respective capacitor. The system then combines the output signals from the capacitors to obtain a combined voltage signal. Next, the system transmits the combined voltage signal over the wire. The transmitted signals can then be received by a hysteresis receiver which is coupled to the wire through a coupling capacitor.Type: GrantFiled: April 12, 2010Date of Patent: August 14, 2012Inventors: Jae-sun Seo, Ronald Ho, Robert J. Drost, Robert D. Hopkins
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Patent number: 8183593Abstract: A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.Type: GrantFiled: October 16, 2009Date of Patent: May 22, 2012Assignee: Oracle America, Inc.Inventors: Robert J. Drost, Robert D. Hopkins, Alex Chow
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Publication number: 20120114032Abstract: A device includes a semiconductor die having a surface, a plurality of proximity connectors proximate to the surface, and a circuit coupled to at least one of the plurality of proximity connectors. The semiconductor die is configured to communicate voltage-mode signals through capacitive coupling using one or more of the plurality of proximity connectors. The circuit also includes a filter with a capacitive-summing junction to equalize the signals.Type: ApplicationFiled: December 30, 2011Publication date: May 10, 2012Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Ronald Ho, Robert D. Hopkins, William S. Coates, Robert J. Drost
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Patent number: 8130821Abstract: An integrated circuit containing a communication channel is described. This communication channel includes a transmit circuit configured to transmit signals using a voltage-mode driver, a receive circuit, and a capacitive link that couples the transmit circuit to the receive circuit. The communication channel includes a filter with a capacitive-summing junction to equalize signals communicated between the transmit circuit and the receive circuit.Type: GrantFiled: May 18, 2006Date of Patent: March 6, 2012Assignee: Oracle America, Inc.Inventors: Robert D. Hopkins, Ronald Ho, William S. Coates, Robert J. Drost
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Patent number: 8102020Abstract: A device includes a semiconductor die having a surface, a plurality of proximity connectors proximate to the surface, and a circuit coupled to at least one of the plurality of proximity connectors. The semiconductor die is configured to communicate voltage-mode signals through capacitive coupling using one or more of the plurality of proximity connectors. The circuit also includes a filter with a capacitive-summing junction to equalize the signals.Type: GrantFiled: May 18, 2006Date of Patent: January 24, 2012Assignee: Oracle America, Inc.Inventors: Ronald Ho, Robert D. Hopkins, William S. Coates, Robert J. Drost
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Patent number: 8098079Abstract: Embodiments of a circuit for use with an inter-chip connection that has a variable complex impedance (which can be conductive, capacitive or both), a system that includes the circuit, and a communication technique are described. This inter-chip connection may be formed between a microspring or an anisotropic film and a metal connector on or proximate to a surface of a chip. Moreover, the circuit may mitigate signal distortion associated with the variable complex impedance. For example, the circuit may include an internal impedance that is electrically coupled in series with the metal connector, and that has an impedance which dominates the variable complex impedance over a range of operating frequencies. Separately or additionally, the circuit may be adapted to correct for the signal distortion.Type: GrantFiled: April 17, 2009Date of Patent: January 17, 2012Assignee: Oracle America, Inc.Inventors: Robert J. Drost, Robert D. Hopkins, Alex Chow
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Publication number: 20110248750Abstract: Some embodiments of the present invention provide techniques and systems for high-bandwidth on-chip communication. During operation, the system receives an input voltage signal which is to be transmitted over a wire in a chip. The system then generates one or more modified voltage signals from the input voltage signal. Next, the system drives each of the voltage signals (i.e., the input voltage signal and the one or more modified voltage signals) through a respective capacitor. The system then combines the output signals from the capacitors to obtain a combined voltage signal. Next, the system transmits the combined voltage signal over the wire. The transmitted signals can then be received by a hysteresis receiver which is coupled to the wire through a coupling capacitor.Type: ApplicationFiled: April 12, 2010Publication date: October 13, 2011Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Jae-sun Seo, Ronald Ho, Robert J. Drost, Robert D. Hopkins
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Publication number: 20110089540Abstract: A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.Type: ApplicationFiled: October 16, 2009Publication date: April 21, 2011Applicant: SUN MICROSYSTEMS, INC.Inventors: Robert J. Drost, Robert D. Hopkins, Alex Chow
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Patent number: 7871833Abstract: A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.Type: GrantFiled: November 9, 2009Date of Patent: January 18, 2011Assignee: Oracle America, Inc.Inventors: Alex Chow, Robert D. Hopkins, Justin M. Schauer
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Publication number: 20100264954Abstract: Embodiments of a circuit for use with an inter-chip connection that has a variable complex impedance (which can be conductive, capacitive or both), a system that includes the circuit, and a communication technique are described. This inter-chip connection may be formed between a microspring or an anisotropic film and a metal connector on or proximate to a surface of a chip. Moreover, the circuit may mitigate signal distortion associated with the variable complex impedance. For example, the circuit may include an internal impedance that is electrically coupled in series with the metal connector, and that has an impedance which dominates the variable complex impedance over a range of operating frequencies. Separately or additionally, the circuit may be adapted to correct for the signal distortion.Type: ApplicationFiled: April 17, 2009Publication date: October 21, 2010Applicant: SUN MICROSYSTEMS, INC.Inventors: Robert J. Drost, Robert D. Hopkins, Alex Chow
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Publication number: 20100176878Abstract: A capacitively and conductively coupled multiplexer (C3mux) circuit is described. This C3mux circuit includes a set of nonlinear coupling capacitors, such as metal-oxide-semiconductor (MOS) transistors, that can multiplex multiple input signals while minimizing the parasitic capacitance penalty associated with the ‘off’ paths. In particular, the capacitance of a given MOS transistor depends on whether its channel is present or absent. Furthermore, this channel is formed based on whether the gate-to-source and drain voltages for the MOS transistor are greater than the MOS transistor's threshold voltage. Note that the capacitance of the MOS transistors in the C3mux circuit is low for the unselected inputs. Consequently, the parasitic loading and the delay increase slowly as a function of the number of inputs. Moreover, the conductive feedback can be used to maintain a DC level of the input signals.Type: ApplicationFiled: January 12, 2009Publication date: July 15, 2010Applicant: SUN MICROSYSTEMS, INC.Inventors: Robert J. Drost, Alex Chow, Robert D. Hopkins
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Patent number: 7750709Abstract: One embodiment of the present invention provides a system that biases a floating node within an integrated circuit. During operation, the system first identifies the floating node within the integrated circuit to be biased. The system then determines a desired bias voltage. Next, the system couples a low-power bias source to the floating node to supply the desired bias voltage, wherein the floating node is biased without stopping data transmission through the floating node during biasing.Type: GrantFiled: January 5, 2007Date of Patent: July 6, 2010Assignee: Oracle America, Inc.Inventors: Justin M. Schauer, Robert D. Hopkins
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Publication number: 20100060299Abstract: A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.Type: ApplicationFiled: November 9, 2009Publication date: March 11, 2010Applicant: SUN MICROSYSTEMS, INC.Inventors: Alex Chow, Robert D. Hopkins, Justin M. Schauer