Patents by Inventor Robert D. Norman

Robert D. Norman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9552311
    Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Robert D. Norman, Vinod C. Lakhani
  • Publication number: 20140281178
    Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.
    Type: Application
    Filed: June 2, 2014
    Publication date: September 18, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Robert D. Norman, Vinod C. Lakhani
  • Patent number: 8745355
    Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Robert D. Norman, Vinod C. Lakhani
  • Patent number: 8369145
    Abstract: A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The controller is adapted to implement the program to provide instructions used to program and erase nonvolatile memory cells. A method embodiment comprises loading a program into memory upon powering up a memory system, and implementing the program using a controller, including programming and erasing multi-bit nonvolatile memory cells.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: February 5, 2013
    Assignee: Round Rock Research, LLC
    Inventors: Robert D. Norman, Christophe J. Chevallier
  • Publication number: 20120192018
    Abstract: A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The controller is adapted to implement the program to provide instructions used to program and erase nonvolatile memory cells. A method embodiment comprises loading a program into memory upon powering up a memory system, and implementing the program using a controller, including programming and erasing multi-bit nonvolatile memory cells.
    Type: Application
    Filed: March 2, 2012
    Publication date: July 26, 2012
    Applicant: Round Rock Research, LLC
    Inventors: Robert D. Norman, Christophe J. Chevallier
  • Patent number: 8130549
    Abstract: A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The controller is adapted to implement the program to provide instructions used to program and erase nonvolatile memory cells. A method embodiment comprises loading a program into memory upon powering up a memory system, and implementing the program using a controller, including programming and erasing multi-bit nonvolatile memory cells.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: March 6, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Robert D. Norman, Christophe J. Chevallier
  • Patent number: 8125834
    Abstract: A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: February 28, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Karl M. J. Lofgren, Jeffrey Donald Stai, Anil Gupta, Robert D. Norman, Sanjay Mehrotra
  • Patent number: 7839685
    Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: November 23, 2010
    Assignee: SanDisk Corporation
    Inventors: Daniel L. Auclair, Jeffrey Craig, John S. Mangan, Robert D. Norman, Daniel C. Guterman, Sanjay Mehrotra
  • Patent number: 7688643
    Abstract: A memory system includes an array of solidstate memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: March 30, 2010
    Assignee: SanDisk Corporation
    Inventors: Karl M. J. Lofgren, Jeffrey Donald Stai, Anil Gupta, Robert D. Norman, Sanjay Mehrotra
  • Publication number: 20100064098
    Abstract: A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon.
    Type: Application
    Filed: November 16, 2009
    Publication date: March 11, 2010
    Inventors: Karl M. J. Lofgren, Jeffrey Donald Stai, Anil Gupta, Robert D. Norman, Sanjay Mehrotra
  • Publication number: 20100020616
    Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
    Type: Application
    Filed: October 1, 2009
    Publication date: January 28, 2010
    Inventors: Daniel L. Auclair, Jeffrey Craig, John S. Mangan, Robert D. Norman, Daniel C. Guterman, Sanjay Mehrotra
  • Patent number: 7616484
    Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: November 10, 2009
    Assignee: SanDisk Corporation
    Inventors: Daniel L. Auclair, Jeffrey Craig, John S. Mangan, Robert D. Norman, Daniel C. Guterman, Sanjay Mehrotra
  • Patent number: 7548461
    Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: June 16, 2009
    Assignee: SanDisk Corporation
    Inventors: Daniel L. Auclair, Jeffrey Craig, John S. Mangan, Robert D. Norman, Daniel C. Guterman, Sanjay Mehrotra
  • Publication number: 20090089536
    Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.
    Type: Application
    Filed: September 24, 2008
    Publication date: April 2, 2009
    Inventors: Robert D. Norman, Vinod C. Lakhani
  • Patent number: 7492660
    Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: February 17, 2009
    Assignee: SanDisk Corporation
    Inventors: Eliyahou Harari, Robert D. Norman, Sanjay Mehrotra
  • Patent number: 7460399
    Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: December 2, 2008
    Assignee: SanDisk Corporation
    Inventors: Eliyahou Harari, Robert D. Norman, Sanjay Mehrotra
  • Patent number: 7457997
    Abstract: An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: November 25, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Robert D. Norman, Christophe J. Chevallier
  • Patent number: 7447069
    Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: November 4, 2008
    Assignee: SanDisk Corporation
    Inventors: Eliyahou Harari, Robert D. Norman, Sanjay Mehrotra
  • Patent number: 7444458
    Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: October 28, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Robert D. Norman, Vinod C. Lakhani
  • Patent number: 7437631
    Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: October 14, 2008
    Assignee: SanDisk Corporation
    Inventors: Daniel L. Auclair, Jeffrey Craig, John S. Mangan, Robert D. Norman, Daniel C. Guterman, Sanjay Mehrotra