Abstract: Systems and methods for low level central plant optimization are provided. A controller for the central plant uses binary optimization to determine one or more feasible on/off configurations for equipment of the central plant that satisfy operating constraints and meet a thermal energy load setpoint. The controller determines optimum operating setpoints for each feasible on/off configuration and generates operating parameters including at least one of the feasible on/off configurations and the optimum operating setpoints. The operating parameters optimize an amount of energy consumed by the central plant equipment. The controller outputs the generated operating parameters via a communications interface for use in controlling the central plant equipment.

Abstract: An optimization system for a central plant includes a processing circuit configured to receive load prediction data indicating building energy loads and utility rate data indicating a price of one or more resources consumed by equipment of the central plant to serve the building energy loads. The optimization system includes a high level optimization module configured to generate an objective function that expresses a total monetary cost of operating the central plant over an optimization period as a function of the utility rate data and an amount of the one or more resources consumed by the central plant equipment. The high level optimization module is configured to optimize the objective function over the optimization period subject to load equality constraints and capacity constraints on the central plant equipment to determine an optimal distribution of the building energy loads over multiple groups of the central plant equipment.

Abstract: A controller for a chiller includes processing electronics configured to detect a plurality of surge events. The processing electronics create a surge map by calculating and plotting a point for each detected surge event in an at least two dimensional coordinate system. The surge map is displayed through the use of an electronic display system. The surge map describes at least three conditions of the chiller when the surge event was detected through the use of axis and non-axis representations. The processing electronics are further configured to control at least one setpoint for the chiller using the calculated surge map.

Abstract: A method for detecting and responding to disturbances in a HVAC system using a noisy measurement signal and a signal filter is provided. The method includes detecting a deviation in the noisy measurement signal, resetting the filter in response to a detected deviation exceeding a noise threshold, filtering the noisy measurement signal using the signal filter to determine an estimated state value, and determining that a disturbance has occurred in response to the estimated state value crossing a disturbance threshold. In some embodiments, the method further includes performing one or more control actions in response to the detection of a disturbance.

Abstract: A controller for a chiller includes processing electronics configured to detect a plurality of surge events. The processing electronics calculate a point for each detected surge event in at least a three dimensional coordinate system. The three dimensional coordinate system describes at least three conditions of the chiller when the surge event was detected. The processing electronics are configured to calculate a surface map for the at least three dimensional coordinate system using the calculated points. The processing electronics are further configured to control at least one setpoint for the chiller using the calculated surface map.

Abstract: A controller for a chiller includes processing electronics configured to detect a plurality of surge events. The processing electronics create a surge map by calculating and plotting a point for each detected surge event in an at least two dimensional coordinate system. The surge map is displayed through the use of an electronic display system. The surge map describes at least three conditions of the chiller when the surge event was detected through the use of axis and non-axis representations. The processing electronics are further configured to control at least one setpoint for the chiller using the calculated surge map.

Abstract: A refrigeration system includes a compressor, a condenser, an expansion device, an evaporator, and an additional refrigerant vessel connected in a closed refrigerant loop. The additional refrigerant vessel is connected to the condenser at the high pressure side by a first valve and to the evaporator at a low pressure side by a second valve. A controller controls operation of the first valve and the second valve. Only one of the first valve and the second valve may be open at the same time. Refrigerant from the additional refrigerant vessel may be added to the closed refrigerant loop when the controller receives a low refrigerant level indication of in the evaporator. Refrigerant may also be removed from the closed refrigerant loop when the controller receives a high refrigerant level indication in the evaporator.

Abstract: A data structure and method of use thereof for encoding video information are described. Macroblock parameters are initialized, and it is determined whether an operating point is selected. If the operating point is selected, then the following occurs: each quad of nodes of a first node level are obtained and a check for merger is done on them; each quad of nodes of a second node level is obtained and a check for merger is done on them; nodes of a third node level are obtained and check for merger is done on them; nodes of a fourth node level are obtained and a check for merger is done on them; and modes are assigned responsive to cost of combinations of encoding modes associated with possible mergers.

Abstract: Method and apparatus for processing scalable content having a base layer and at least one enhancement layer is described. In one example, static logic having decoder logic and system monitor logic is provided. Programmable logic having a plurality of reconfigurable slots is also provided. The decoder logic includes a base layer processor for processing the base layer of the scalable content. The system monitor logic is configured to dynamically reconfigure at least one of the plurality of reconfigurable slots with at least one enhancement block for processing the at least one enhancement layer of the scalable content.

Abstract: A controller for a chiller includes processing electronics configured to detect a plurality of surge events. The processing electronics calculate a point for each detected surge event in at least a three dimensional coordinate system. The three dimensional coordinate system describes at least three conditions of the chiller when the surge event was detected. The processing electronics are configured to calculate a surface map for the at least three dimensional coordinate system using the calculated points. The processing electronics are further configured to control at least one setpoint for the chiller using the calculated surface map.

Abstract: Method and apparatus for communication between hardware blocks configured in a programmable logic device (PLD) and a computation device external to the PLD is described. A bus controller is provided for receiving words from the computation device. Each of the words includes an address component and a data component. A first-in-first-out buffer (FIFO) is configured for communication with the bus controller to store the words. A processing engine is provided having a memory space associated with the hardware blocks and being configured to receive a word at a top of the FIFO. An address decoder is provided for decoding the address component of the word at the top of the FIFO to obtain an address of a memory location in the memory space. A strobe generator is provided for coupling a strobe signal to the processing engine. The strobe signal is configured to store the word in the memory location.

Abstract: Various approaches for embedding identifier information in a configuration bitstream for a programmable logic device (PLD) are disclosed. In various embodiments, the bits in the configuration bitstream that are unused in implementing a the design are identified. The identifier information is encrypted, and a subset of the unused bits are selected using a pseudo-random function. The encrypted identifier information is placed in the selected subset of unused bits. Decryption is accomplished by reversing the encryption approach.

Abstract: An aspect of the invention relates to communication between a first processing element and a second processing element. A first-in-first-out circuit (FIFO) includes a data input port, a data output port, an object-sent port, an object-end port, a memory, and control logic. The data input port is coupled to the first processing element. The data output port is coupled to the second processing element. The object-sent port is configured to receive an object-sent signal from the first processing element. The object-end port is configured to send an object-end signal to the second processing element. The memory is configured to store objects, each of the objects include a plurality of data words. The control logic is configured to control reading and writing to the memory, processing the object sent signal, and generating the object end signal.

Abstract: Circuit arrangements and methods for real-time image resizing and image rotation. Line buffers are used for storage of lines of pixel values for both resizing and rotation. A first one of the line buffers receives input pixel values, and the line buffers are coupled in a chain such that line buffer i receives pixel values from line buffer i−1. The lines of pixel values are moved from line buffer i to line buffer i+1 as the pixel values are processed for resizing or rotation.

Abstract: A one-dimensional wavelet system and method. In various embodiments, computation engines are set forth for forward and inverse transforms in a wavelet system. The computation engine includes a plurality of register banks having input ports arranged to receive input sample values and a multiplexer coupled to the output ports of the register banks. A processing unit is configured to perform the forward or inverse wavelet transform for data values that are sequenced through the register banks and multiplexer by a control unit. The computation unit is adaptable to implement discrete wavelet transform, discrete wavelet packet, and custom wavelet trees.

Abstract: Two-dimensional discrete wavelet transform analysis and synthesis banks. In various embodiments, a cascade combination of two one-dimensional wavelet transforms is implemented, along with a set of memory buffers between the two stages. The memory buffers store intermediate results between the stages of the two-dimensional discrete wavelet transform, thereby eliminating off-chip memory references.