Patents by Inventor Robert E. Gough
Robert E. Gough has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11768791Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.Type: GrantFiled: May 2, 2022Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: David J. Harriman, Reuven Rozic, Maxim Dan, Prashant Sethi, Robert E. Gough, Shanthanand Kutuva Rabindranath
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Patent number: 11567896Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.Type: GrantFiled: June 30, 2020Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Guy G. Sotomayor, Andrew D. Henroid, Robert E. Gough, Tod F. Schiff
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Publication number: 20220334994Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.Type: ApplicationFiled: May 2, 2022Publication date: October 20, 2022Applicant: Intel CorporationInventors: David J. Harriman, Reuven Rozic, Maxim Dan, Prashant Sethi, Robert E. Gough, Shanthanand Kutuva Rabindranath
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Patent number: 11321264Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.Type: GrantFiled: December 29, 2020Date of Patent: May 3, 2022Assignee: INTEL CORPORATIONInventors: David J. Harriman, Reuven Rozic, Maxim Dan, Prashant Sethi, Robert E. Gough, Shanthanand Kutuva Rabindranath
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Publication number: 20210232522Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.Type: ApplicationFiled: December 29, 2020Publication date: July 29, 2021Applicant: Intel CorporationInventors: David J. Harriman, Reuven Rozic, Maxim Dan, Prashant Sethi, Robert E. Gough, Shanthanand Kutuva Rabindranath
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Publication number: 20210208901Abstract: During a computing system boot sequence, reference firmware provided by a computing system component supplies Advanced Component and Peripheral Interface (ACPI) code that generates ACPI tables and definition blocks to a bootloader. During a boot sequence, the reference firmware receives an indication from the bootloader which components the reference firmware is to initialize. As part of component initialization performed by the reference firmware, the reference firmware populates hand-off data structures (e.g., hand-off blocks (HOBs)) with ACPI code (AML code) that, when executed by the bootloader, generates and populates ACPI tables (e.g., DSDT and SSDT tables) and definition blocks with information pertinent to the initialization and runtime management of computing system components. Component initialization and runtime configuration workarounds can be implemented in the bootloader incorporating reference firmware updates provided by the component vendor.Type: ApplicationFiled: March 24, 2021Publication date: July 8, 2021Applicant: Intel CorporationInventors: Subrata Banik, Aamir Bohra, Vincent Zimmer, Robert E. Gough, Xiang Ma, Jabeena Begum Gaibusab
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Patent number: 10877915Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.Type: GrantFiled: September 30, 2016Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: David J. Harriman, Reuven Rozic, Maxim Dan, Prashant Sethi, Robert E. Gough, Shanthanand Kutuva Rabindranath
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Publication number: 20200334193Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.Type: ApplicationFiled: June 30, 2020Publication date: October 22, 2020Inventors: Ankush Varma, Krishnakanth V. Sistla, Guy G. Sotomayor, Andrew D. Henroid, Robert E. Gough, Tod F. Schiff
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Patent number: 10706004Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.Type: GrantFiled: November 14, 2017Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Guy G. Sotomayor, Andrew D. Henroid, Robert E. Gough, Tod F. Schiff
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Patent number: 10571992Abstract: An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode.Type: GrantFiled: June 27, 2017Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Robert E. Gough, Mazen G. Gedeon, Barnes Cooper, Basavaraj B. Astekar, Sean C. Dardis
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Patent number: 10185385Abstract: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.Type: GrantFiled: June 13, 2016Date of Patent: January 22, 2019Assignee: Intel CorporationInventors: Paul S. Diefenbaugh, Robert E. Gough, Yuval Bachrach, Mikal C. Hunsaker, Rafi Ben-Tal, Ilan Pardo, Gideon Prat, David J. Harriman
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Patent number: 10182398Abstract: An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.Type: GrantFiled: March 8, 2017Date of Patent: January 15, 2019Assignee: Intel CorporationInventors: Jaya L. Jeyaseelan, Jim Walsh, Robert E. Gough, Barnes Cooper, Neil W. Songer
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Patent number: 10146291Abstract: A serial point-to-point link interface to enable communication between a processor and a device, the high speed serial point-to-point link interface including a transmitter to transmit serial data, a receiver to deserialize serial data, and control logic to implement a protocol stack. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is maintained, and a second off state, in which the supply voltage is not to be provided to the device. The protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device. The protocol stack further provides for accessing the device prior to expiration of the default recovery time to complete the transition based on a device-advertised recovery time.Type: GrantFiled: December 24, 2015Date of Patent: December 4, 2018Assignee: Intel CorporationInventors: Mahesh Wagh, Robert E. Gough
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Patent number: 10139889Abstract: A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.Type: GrantFiled: December 24, 2015Date of Patent: November 27, 2018Assignee: Intel CorporationInventors: Mahesh Wagh, Robert E. Gough
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Patent number: 9965293Abstract: Techniques for adaptive interface support are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to execute a basic input/output system (BIOS), determine a respective impedance state for each of one or more pins in an M.2 physical interface, determine an interface type for a peripheral device coupled with the M.2 physical interface based on the impedance states for the one or more pins, and control an operational state of the peripheral device during execution of the BIOS, based on the interface type for the peripheral device. Other embodiments are described and claimed.Type: GrantFiled: December 30, 2016Date of Patent: May 8, 2018Assignee: INTEL CORPORATIONInventors: Nathaniel L. Desimone, Robert E. Gough, Sean C. Dardis
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Patent number: 9961478Abstract: The present disclosure is directed to logging random “chirps” of IoT devices and rebroadcasting these chirps to other devices on demand. An apparatus consistent with the present disclosure includes a transmitter to communicate with a network of wireless-communication-enabled devices. The apparatus also includes a receiver to detect communications transmitted from the wireless-communication-enabled device. Further, the apparatus includes control unit logic to tally the number of electrical signals emitted from each wireless-communication-enabled device. In addition, the apparatus includes memory to store the number of emitted electrical signals. The apparatus further includes a power unit electrically coupled to the transmitter, receiver, and memory.Type: GrantFiled: August 4, 2014Date of Patent: May 1, 2018Assignee: Intel CorporationInventors: David W. Browning, Kristoffer D. Fleming, Robert E. Gough, Guy G. Sotomayor, Vasudev Bibikar, Ankush Varma
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Publication number: 20180067892Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.Type: ApplicationFiled: November 14, 2017Publication date: March 8, 2018Inventors: Ankush Varma, Krishnakanth V. Sistla, Guy G. Sotomayor, Andrew D. Henroid, Robert E. Gough, Tod F. Schiff
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Publication number: 20180046240Abstract: An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode.Type: ApplicationFiled: June 27, 2017Publication date: February 15, 2018Inventors: Robert E. GOUGH, Mazen G. GEDEON, Barnes COOPER, Basavaraj B. ASTEKAR, Sean C. DARDIS
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Patent number: 9891691Abstract: Methods and apparatus relating to reducing pin count requirements for implementation of interconnect idle state(s) are described. In one embodiment, logic receives a general purpose input signal on a signal pin of an Input/Output (I/O) complex logic in response to a control signal. An I/O device (e.g., coupled to the I/O complex logic) enters a low power consumption state in response to the control signal. The logic receives a wake signal on the signal pin of the I/O complex logic and the I/O device exits the low power consumption state in response to the wake signal. Other embodiments are also claimed and disclosed.Type: GrantFiled: September 27, 2013Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Naveen Gopal Reddy, Bharath Kumar, Robert E. Gough
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Patent number: 9842082Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.Type: GrantFiled: February 27, 2015Date of Patent: December 12, 2017Assignee: Intel CorporationInventors: Ankush Varma, Krishnakanth V. Sistla, Guy G. Sotomayor, Andrew D. Henroid, Robert E. Gough, Tod F. Schiff