Patents by Inventor Robert E. Gough

Robert E. Gough has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8549205
    Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Mahesh Wagh, Robert E. Gough, James E. Jaussi
  • Publication number: 20130132755
    Abstract: A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 23, 2013
    Inventors: Barnes Cooper, Jaya L. Jeyaseelan, Robert E. Gough
  • Publication number: 20130007483
    Abstract: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Inventors: Paul S. Diefenbaugh, Robert E. Gough, Yuval Bachrach, Mikal C. Hunsaker, Rafi Ben-Tal, Ilan Pardo, Gideon Prat, David J. Harriman
  • Patent number: 8341445
    Abstract: A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: December 25, 2012
    Assignee: Intel Corporation
    Inventors: Barnes Cooper, Jaya L. Jeyaseelan, Robert E. Gough
  • Patent number: 8161322
    Abstract: Methods and apparatus to initiate a basic input/output system (BIOS) recovery are disclosed herein. An example BIOS recovery module includes a memory storing one or more signatures to be detected by a detector of a BIOS implemented on a computing platform; and a connector to couple the module to a data display channel of the computing platform, wherein a BIOS recovery mechanism of the BIOS is to initiate in response to the detector detecting the one or more signatures of the module via the data display channel.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: April 17, 2012
    Assignee: Intel Corporation
    Inventor: Robert E. Gough
  • Publication number: 20110276816
    Abstract: A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
    Type: Application
    Filed: July 19, 2011
    Publication date: November 10, 2011
    Inventors: Barnes Cooper, Jaya L. Jeyaseelan, Robert E. Gough
  • Patent number: 7984314
    Abstract: A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
    Type: Grant
    Filed: September 29, 2007
    Date of Patent: July 19, 2011
    Assignee: Intel Corporation
    Inventors: Barnes Cooper, Jaya L. Jeyaseelan, Robert E. Gough
  • Publication number: 20110138220
    Abstract: Methods and apparatus to initiate a basic input/output system (BIOS) recovery are disclosed herein. An example BIOS recovery module includes a memory storing one or more signatures to be detected by a detector of a BIOS implemented on a computing platform; and a connector to couple the module to a data display channel of the computing platform, wherein a BIOS recovery mechanism of the BIOS is to initiate in response to the detector detecting the one or more signatures of the module via the data display channel.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 9, 2011
    Inventor: Robert E. Gough
  • Publication number: 20100169685
    Abstract: For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Robert E. Gough, Seh W. Kwa, Neil W. Songer, Jaya L. Jeyaseelan, Barnes Cooper
  • Publication number: 20100169684
    Abstract: For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Jaya L. Jeyaseelan, Jim Walsh, Robert E. Gough, Barnes Cooper, Neil W. Songer
  • Publication number: 20080288798
    Abstract: A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.
    Type: Application
    Filed: September 29, 2007
    Publication date: November 20, 2008
    Inventors: Barnes Cooper, Jaya L. Jeyaseelan, Robert E. Gough