Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

Abstract: A four-channel by two ranks-per-channel memory module includes four independent memory channels and dual-channel memory devices. The channels of the dual-channel memory module devices may be accessed independently. Thus, the four channels for accessing the memory module may each concurrently access, via a one of the two channels of the memory devices, a respective first rank and a second rank. Data buffer devices on the memory module communicate data between the two ranks and the channels. The data buffer devices multiplex/demultiplex (a.k.a., interleave/deinterleave) communication between the channels and the ranks so that the channels operate at a greater bandwidth (e.g., quad-data rate—QDR) than the memory devices (e.g., double-data rate—DDR). The data buffer devices also retime and/or redistribute data strobe signals communicated between the memory devices and the channels.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract: A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract: A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract: A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract: An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

Abstract: A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract: A latency controller within an integrated circuit device retimes command-stream-triggered control and timing signals into endpoint timing domains having respective time-varying phase offsets relative to a reference clock by iteratively estimating and logging the phase offsets independently of commands streaming into the integrated circuit device.

Abstract: An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of a data interface circuit of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

Abstract: A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.