Abstract: A pleisiochronous repeater system and components thereof are disclosed. In one particular exemplary embodiment, a pleisiochronous repeater system component may be realized as a receiver circuit comprising a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a data clock signal. The receiver circuit may also comprise a divider circuit that generates a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.

Abstract: An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

Abstract: Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter.

Abstract: A receiver includes clocked, differential equalization circuitry to compensate for signal attenuation that varies with the frequency of the input signal received over a respective communication channel. The incoming signal is split into filtered and unfiltered signal components. Separate current-steering transistors coupled in parallel amplify the filtered and unfiltered components and sum the results. The filter or filters used to separate the signal components may be tunable, e.g. using voltage-controlled filter components. The ratio of device sizes for the current-steering transistors sets the magnitude of the boost applied to high-frequency components. The embodiments include adjustable or programmable current-steering networks to facilitate adjustments that accommodate the unique characteristics of individual communication channels.

Abstract: Methods and systems for differential signaling include transmitting differential signals over N conductors, where N is greater than 2, from a sender to a receiver. The sender includes multiple transmitters that receive digital data and produce output signals based on the digital data. The output signals result in currents on conductors between the transmitters and multiple receivers. For any given symbol, the sum of the currents on the conductors is preferably equal to zero. In addition, a voltage difference preferably exists across the input terminals of each receiver. Methods and systems for coding binary data for transmission over a multi-conductor differential signaling system include converting input binary data into symbol numbers, converting the symbol numbers into valid drive words for a multi-conductor differential signaling system, and inputting the valid drive words to multiple differential transmitters.