Patents by Inventor Robert F. Darveaux

Robert F. Darveaux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190371706
    Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.
    Type: Application
    Filed: April 2, 2019
    Publication date: December 5, 2019
    Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
  • Patent number: 10347562
    Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: July 9, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
  • Patent number: 9721872
    Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: August 1, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
  • Patent number: 8383950
    Abstract: A first patterned etch stop layer and a first patterned conductor layer are laminated by a dielectric material to a second patterned etch stop layer and a second patterned conductor layer. As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers, the first and second patterned etch stop layers provide an etch stop for substrate formation etch processes. In this manner, etching of the first and second patterned conductor layers is avoided insuring that impedance is controlled to within tight tolerance.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: February 26, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, Robert F. Darveaux
  • Patent number: 8365611
    Abstract: A bend test method includes bending a flip chip device into a bent configuration, heating the flip chip device, and inspecting the flip chip device for failure. The bend test method is completed in a relatively short amount of time, e.g., within one to three days. Thus, appropriate failure modes in flip chip devices are created in an accelerated manner so that reliability assessment of various flip chip device designs, materials, and process options can be completed in a few days instead of a few months. This greatly reduced development cycle time typically results in a larger market share for new flip chip device products.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: February 5, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Robert F. Darveaux, Christopher J. Berry
  • Patent number: 8129824
    Abstract: A semiconductor device has a substrate. A first die is electrically attached to a first surface of the substrate. A shield spacer having a first and second surface is provided wherein the second surface of the shield spacer is attached to a first surface of the first die. A plurality of wirebonds are attached to the shield spacer and to the substrate. A mold compound is provided for encapsulating the first die, the shield spacer, and the wirebonds.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: March 6, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Roger D. St. Amand, Nozad O. Karim, Joseph M. Longo, Lee J. Smith, Robert F. Darveaux, Jong Ok Chun, Jingkun Mao
  • Patent number: 8017436
    Abstract: A method of forming a package includes forming a circuit pattern on a first carrier and embedding the circuit pattern in a dielectric material on a second carrier. The first carrier is removed and a buildup dielectric material is mounted to the dielectric material and the circuit pattern. Laser-ablated artifacts are formed in the buildup dielectric material and filled with an electrically conductive material to form a buildup circuit pattern. The second carrier is patterned into a stiffener, which provides rigidity to the thin package.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: September 13, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, Bob Shih-Wei Kuo, Jon Gregory Aday, Lee John Smith, Robert F. Darveaux
  • Patent number: 7923645
    Abstract: A first patterned etch stop layer and a first patterned conductor layer are laminated by a dielectric material to a second patterned etch stop layer and a second patterned conductor layer. As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers, the first and second patterned etch stop layers provide an etch stop for substrate formation etch processes. In this manner, etching of the first and second patterned conductor layers is avoided insuring that impedance is controlled to within tight tolerance.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: April 12, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, Robert F. Darveaux
  • Patent number: 7911017
    Abstract: An optical module includes an image sensor having an active area and a window mounted directly to the image sensor above the active area. The optical module further includes a mount mounted to the window, the mount supporting a barrel having a lens assembly. By mounting the window directly to the image sensor and the mount directly to the window, the substrate surface area of the optical module is minimized.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: March 22, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Arsenio de Guzman, Robert F. Darveaux, Young Ho Kim
  • Patent number: 7576401
    Abstract: An optical module includes an image sensor having an active area and a window mounted directly to the image sensor above the active area. The optical module further includes a mount mounted to the window, the mount supporting a barrel having a lens assembly. By mounting the window directly to the image sensor and the mount directly to the window, the substrate surface area of the optical module is minimized.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: August 18, 2009
    Assignee: Amkor Technology, Inc.
    Inventors: Arsenio de Guzman, Robert F. Darveaux, Young Ho Kim
  • Patent number: 7253503
    Abstract: Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A planar metal die pad and planar metal are attached to the second surface of the polyimide sheet. The apertures in the polyimide sheet are juxtaposed to the leads. A package made using the substrate includes an integrated circuit device mounted above the first surface of the polyimide sheet opposite the die pad. Bond wires are connected between the integrated circuit device and the leads through the apertures in the polyimide sheet. An encapsulant material covers the first surface of the polyimide sheet, the integrated circuit device, the bone wires, and the apertures. The die pad and leads are exposed at an exterior surface of the package.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: August 7, 2007
    Assignee: Amkor Technology, Inc.
    Inventors: James M. Fusaro, Robert F. Darveaux, Pablo Rodriguez
  • Patent number: 7126218
    Abstract: A heat slug or spreader is attached directly to a surface of the die in a ball grid array (BGA) package. The heat spreader roughly conforms to the topological profile of the die, underlying substrate, and electrical interconnections between the die and the substrate, such as bond wires. The outer portion of the heat spreader substantially cover the outer portion of the substrate, or alternatively, cover only those portions extending in laterally from the sides of the chip and not the corners. An encapsulant completely covers the heat spreader and die.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: October 24, 2006
    Assignee: Amkor Technology, Inc.
    Inventors: Robert F. Darveaux, Frederick J. G. Hamilton, Bruce M. Guenin, Vincent DiCaprio
  • Patent number: 6833609
    Abstract: Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A planar metal die pad and planar metal are attached to the second surface of the polyimide sheet. The apertures in the polyimide sheet are juxtaposed to the leads. A package made using the substrate includes an integrated circuit device mounted above the first surface of the polyimide sheet opposite the die pad. Bond wires are connected between the integrated circuit device and the leads through the apertures in the polyimide sheet. An encapsulant material covers the first surface of the polyimide sheet, the integrated circuit device, the bond wires, and the apertures. The die pad and leads are exposed at an exterior surface of the package.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: December 21, 2004
    Assignee: Amkor Technology, Inc.
    Inventors: James M. Fusaro, Robert F. Darveaux, Pablo Rodriguez
  • Patent number: 6580159
    Abstract: Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A planar metal die pad and planar metal are attached to the second surface of the polyimide sheet. The apertures in the polyimide sheet are juxtaposed to the leads. A package made using the substrate includes an integrated circuit device mounted above the first surface of the polyimide sheet opposite the die pad. Bond wires are connected between the integrated circuit device and the leads through the apertures in the polyimide sheet. An encapsulant material covers the first surface of the polyimide sheet, the integrated circuit device, the bond wires, and the apertures. The die pad and leads are exposed at an exterior surface of the package.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: June 17, 2003
    Assignee: Amkor Technology, Inc.
    Inventors: James M. Fusaro, Robert F. Darveaux, Pablo Rodriguez
  • Patent number: 6400033
    Abstract: A method and apparatus for reinforcing the solder connections between a semiconductor device and a substrate includes the provision of a rigid frame having a central opening through it, a planar top surface, a bottom surface opposite and parallel to the top surface, and a thickness between the two surfaces to equal to the height of the solder connections. The top surface of the frame is attached to the bottom surface of the semiconductor device at the peripheral edges thereof and outside of a plurality of input/output terminals thereon. The bottom surface of the frame is attached to the top surface of the substrate. The frame reinforces the solder connections between a C4-mounted semiconductor die or a C5-mounted semiconductor package and a substrate against the stresses acting on the connections with bending of the PCB.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: June 4, 2002
    Assignee: Amkor Technology, Inc.
    Inventor: Robert F. Darveaux
  • Patent number: 6331451
    Abstract: Methods of making integrated circuit device packages and substrates for making the packages are disclosed. An embodiment of a method of making a substrate includes providing an unpatterned sheet of polyimide material having a first surface and an opposite second surface. A planar metal layer is attached to the second surface of the polyimide sheet. The metal layer is patterned to form an array of package sites, with each site including a planar die pad and planar leads. Apertures are formed through the polyimide sheet, either before or after attaching the metal layer. Each aperture is juxtaposed with a lead allowing access thereto. A method of making a package using the substrate includes mounting an integrated circuit device above the die pad (e.g., on the substrate or on the die pad through an aperture in the substrate). Bond wires are connected between the integrated circuit device and the leads through the apertures.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: December 18, 2001
    Assignee: Amkor Technology, Inc.
    Inventors: James M. Fusaro, Robert F. Darveaux, Pablo Rodriguez
  • Patent number: 6201305
    Abstract: The invention discloses a method of making solder ball mounting pads on a substrate that have better ball shear performance, ball thermal cycle reliability, ball attach yield, and ball positional tolerances, than the solder ball mounting pads of the prior art. The method includes providing a sheet of material having a layer of metal thereon, and patterning the layer to define a solder ball mounting pad therein. The pad includes a central pad having at least two spokes radiating outward from it. An insulative mask is formed over the metal layer, and an opening is formed in the mask such that the central pad and an inner portion of each of the spokes is exposed therethrough, and an outer portion of each of the spokes is covered by the mask. In one embodiment, the central pad, spokes, and opening in the mask are shaped and arranged with respect to each other such that the pad and exposed portion of the spokes form a radially symmetrical pattern within the opening.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: March 13, 2001
    Assignee: Amkor Technology, Inc.
    Inventors: Robert F. Darveaux, Barry M. Miles, Alexander W. Copia
  • Patent number: 6124637
    Abstract: A grid array assembly method and apparatus uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surfaces wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: September 26, 2000
    Assignee: Amkor Technology, Inc.
    Inventors: Bruce J. Freyman, Robert F. Darveaux
  • Patent number: 5985695
    Abstract: A grid array assembly method uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes or vias in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surface, wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: November 16, 1999
    Assignee: Amkor Technology, Inc.
    Inventors: Bruce J. Freyman, Robert F. Darveaux
  • Patent number: 5859475
    Abstract: A grid array assembly method and apparatus uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surface, wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: January 12, 1999
    Assignee: Amkor Technology, Inc.
    Inventors: Bruce J. Freyman, Robert F. Darveaux