Patents by Inventor Robert F. Darveaux

Robert F. Darveaux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6124637
    Abstract: A grid array assembly method and apparatus uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surfaces wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: September 26, 2000
    Assignee: Amkor Technology, Inc.
    Inventors: Bruce J. Freyman, Robert F. Darveaux
  • Patent number: 5985695
    Abstract: A grid array assembly method uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes or vias in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surface, wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: November 16, 1999
    Assignee: Amkor Technology, Inc.
    Inventors: Bruce J. Freyman, Robert F. Darveaux
  • Patent number: 5859475
    Abstract: A grid array assembly method and apparatus uses a flex circuitry substrate and includes providing a series of conforming flex circuitry substrates, the flex circuitry substrates include bonding pads and metallization on a first surface and, holes in the substrate which define a contact pad array on the opposite surface. The substrates are tested and acceptable, then mounted on a carrier strip with longitudinally aligned apertures. The carrier strip is typically a metal such as copper. The strip with mounted substrates is then passed to a station where an IC die is mounted on the substrate first surface, wire bonds are placed from the die to the bonding pads, and the assembly is encapsulated by auto-molding to form a package body. Subsequently, interconnecting bumps are placed on the contact pads and the assembly is removed from the strip.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: January 12, 1999
    Assignee: Amkor Technology, Inc.
    Inventors: Bruce J. Freyman, Robert F. Darveaux
  • Patent number: 5552636
    Abstract: A discrete element electronic package (100) includes a heat spreader (180) with a cavity (185) for receiving a substrate (110), a substrate (110) mounted within the cavity (185) of the heat spreader (180), a heat-generating semiconductor device (170), such as a power transistor (170), mounted on the substrate (110), and electrical connectors (140) located on the substrate (110) to provide an electrical interface to the semiconductor device (170).
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: September 3, 1996
    Assignee: Motorola, Inc.
    Inventor: Robert F. Darveaux
  • Patent number: 5455446
    Abstract: A plastic leaded semiconductor package (20) has a semiconductor device (614) encapsulated in the package and mounted to a lead frame (612). The lead frame has a plurality of leads (622) that extend beyond the body (610) of the encapsulated package. Each of the plurality of leads is made from a metal having a predetermined coefficient of thermal expansion. A second metal (627) with a different coefficient of thermal expansion is disposed on at least one portion of each of the leads.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: October 3, 1995
    Assignee: Motorola, Inc.
    Inventors: Anthony B. Suppelsa, Robert F. Darveaux, Michael L. Weiss
  • Patent number: 5411199
    Abstract: A method for attaching a shield (102) to a an electronic assembly (116) having a heat sink (110) includes applying solder on the inner walls (104) of the shield (102). Next, the shield (102) is placed over the electronic assembly (116) such that the electronic assembly (116) is covered by the shield (102) and the shield (102) is in mechanical contact with the heat sink (110). Then, the shield (102) and heat sink (110) are heated so that the solder on the inner walls (104) of shield (102) flows and solders the shield (102) to the heat sink (110).
    Type: Grant
    Filed: March 7, 1994
    Date of Patent: May 2, 1995
    Assignee: Motorola, Inc.
    Inventors: Anthony J. Suppelsa, Robert F. Darveaux, Thomas A. Goodwin, Julio Abdala, Henry F. Liebman
  • Patent number: 5325265
    Abstract: A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.
    Type: Grant
    Filed: January 7, 1992
    Date of Patent: June 28, 1994
    Assignees: MCNC, IBM Corporation, Northern Telecom Limited
    Inventors: Iwona Turlik, Arnold Reisman, Deepak Nayak, Lih-Tyng Hwang, Giora Dishon, Scott L. Jacobs, Robert F. Darveaux, Neil M. Poley
  • Patent number: 5203076
    Abstract: A method of attaching an integrated circuit (10) to a substrate (20) starts with electrically interconnecting (14) the integrated circuit on the substrate. Next, a bead of underfill material (22) is provided on the substrate (20) about the periphery (24) of the integrated circuit (10). At least a partial vacuum (34) is then applied to the integrated circuit (10) and the substrate (20) to substantially evacuate the area (18) between the integrated circuit (10) and the substrate (20). Finally, fluid pressure (42) is applied to the integrated circuit (10) and the substrate (20) to force at least a portion of the underfill material (22) into the area (18) between the integrated circuit (10) and the substrate (20).
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: April 20, 1993
    Assignee: Motorola, Inc.
    Inventors: Kingshuk Banerji, Francisco D. Alves, Robert F. Darveaux
  • Patent number: 5152451
    Abstract: A method of soldering leadless components to a printed circuit board without using solder paste is disclosed. A thick layer of solder (42) is plated onto a printed circuit board (40), and an oxide layer (43) is formed by heating. Solder flux (45) is applied to those solder pads that are intended to be reflowed, and components (54) are placed. The printed circuit board is heated, and a solder joint (68) is effected between the components (54) and the circuit board (40), while the unfluxed solder pads (66) do not reflow and remain flat. Solder flux is then applied to the remaining solder pads (66) on the same or the opposite side of the circuit board. Additional components (77) are placed, and the circuit board (40) is reflowed a second time.
    Type: Grant
    Filed: April 1, 1991
    Date of Patent: October 6, 1992
    Assignee: Motorola, Inc.
    Inventors: Robert F. Darveaux, Kingshuk Banerji, Francisco da Costa Alves