Abstract: An electronic x-ray imaging array is provided by combining a two-dimensional photosensitive array with a structured scintillator array, having a common array pattern and suitable alignment marks thereon, by bonding them face-to-face in alignment for direct coupling of x-ray luminescence from the scintillator array to the photosensitive array.

Abstract: A radiation imager comprises a scintillator mated to a photodetector array. An enclosure ring is disposed around the outer sidewalls of the scintillator and an enclosure ring cover hermetically bonded to the ring extends across the scintillator to form a chamber sealably enclosing the scintillator. The enclosure ring cover is substantially impervious to moisture, is radiation transmissive, and minimizes scattering of light from the scintillator. The cover may be optically reflective or light absorptive. The chamber is evacuated to draw the cover in towards the photodetector array and thus to ensure close contact between the cover and the scintillator and between the scintillator and the photodetector array. Desiccant can be disposed in the chamber to provide additional protection against moisture absorption by the scintillator.

Abstract: A thin film transistor includes a two-layer gate metallization comprising a relatively thin first layer of a first conductor and a relatively thick second layer of a second conductor with the second conductor being capable of being etched with an etchant that produces substantially no etching of the first conductor layer. During device fabrication, the thick gate metallization layer (second conductor) is selectively etched until all of that material is removed in the openings in the mask. The thin lower layer (first conductor) is then etched with a minimum of etching into the substrate. The gate dielectric and subsequent layers deposited over this gate metallization have high integrity and highly reliable continuity because of the sloped nature of the gate metallization sidewalls, and because of the shallow gate metallization topography due to minimization of substrate etching during gate metallization patterning.