Abstract: A method and system of temperature compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of temperature compensation.

Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

Abstract: A method and system of voltage compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of voltage compensation.

Abstract: A fast light off flow-through ceramic substrate is provided that is particularly adapted for use as a catalytic converter. The substrate is formed from a body of ceramic material having axially opposing inlet and outlet ends for receiving and expelling the flow of automotive exhaust gas, respectively. The body contains a network of walls coated with a catalyst that define axially-oriented flow-through cell channels. The average thermal mass (ATM1) of a first axial region of the walls adjacent to the inlet end is at least 20% less than the average thermal mass (ATMTOT) of all of the walls. The lower average thermal mass of the walls in the first region advantageously shortens the light off time for the catalyst within the substrate to effectively neutralize automotive pollutants. The reduction of the average thermal mass in only the first axial region of the walls advantageously maintains the strength of the resulting body of ceramic material, and further increases the cool down time of the body.

Abstract: A method for making a chrome photo-mask is disclosed. A photo-mask blank is activated with activator on its upper surface for electroless chrome plating Next, the activated photo-mask blank is then immersed in the electroless chrome plating solution for being coated with a thin chrome layer. The electroless chrome plating process will continue until a desired thickness is formed. Preferably, an electro-plating process is employed after the growth of an initial electroless chrome layer. Then, the photo-mask blank with the chrome layer is subject to oxidation for forming an antireflection layer on the chrome layer. After the antireflective layer is successively formed, a resist film is formed on the antireflective layer. The resist film is then patterned in accordance with the predetermined pattern. Next, the antireflective layer and the chromium layer are dry-etched or wet-etched through openings in the patterned resist film. The resist film is subsequently stripped to form the desired photo-mask.

Abstract: A stabilization component for substrate potential regulation for an integrated circuit device. A comparator is coupled to a charge pump to control the charge pump to drive a substrate potential. A stabilization component is coupled to the comparator and is operable to correct an over-charge of the substrate by shunting current from the substrate.

Abstract: A method and system of temperature compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of temperature compensation.

Abstract: A method and system of voltage compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of voltage compensation.

Abstract: A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor.