Abstract: A sequencing capture array for identifying mutations in Multiple Myeloma is disclosed. Also disclosed are targeted next generation sequencing methods for identifying SNV, CNV, and translocation mutations in Multiple Myeloma tumor cells. A capture array representing fewer than 500 genes implicated in Multiple Myeloma can be used to analyze tumor mutations and create a personalized treatment plan for a Multiple Myeloma patient. Analytical methods are presented that allow tumor mutations to be elucidated with coverage at a sequencing depth of no more than 500×, or as low as 100×, with optimal efficiency achieved at a sequencing depth of about 300×.

Abstract: Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.

Abstract: Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.

Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

Abstract: A sequencing capture array for identifying mutations in Multiple Myeloma is disclosed. Also disclosed are targeted next generation sequencing methods for identifying SNV, CNV, and translocation mutations in Multiple Myeloma tumor cells. A capture array representing fewer than 500 genes implicated in Multiple Myeloma can be used to analyze tumor mutations and create a personalized treatment plan for a Multiple Myeloma patient. Analytical methods are presented that allow tumor mutations to be elucidated with coverage at a sequencing depth of no more than 500×, or as low as 100×, with optimal efficiency achieved at a sequencing depth of about 300×.

Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

Abstract: An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.

Abstract: An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.

Abstract: According to an embodiment of the invention, a method and apparatus for DC voltage conversion are described. According to one embodiment, a voltage converter comprises a current mirror, the current mirror being coupled with a power source; a first transistor device coupled with a bias generator to receive a bias voltage; a second transistor device coupled between the current mirror and the first transistor device; and an output transistor device, a gate of the output transistor device being coupled with a gate of the second transistor device and to the current mirror.

Abstract: A substance and method for treating a subterranean formation using hydraulic fracturing. A non-metallic, substantially deformable, proppant particle is “elastically flexible” or “plastically compressible” and adapted for use at concentrations which will substantially create a partial monolayer.

Abstract: A braking system for a movable unit which travels along a cable includes a plate of conductive material extending from the cable to define a braking zone having a start and an end along at least a portion of the cable. There is a brake unit movable along the cable and positionable at the start of the braking zone. The brake unit has magnets positionable on opposite sides of the conductive material. The brake unit is engagable by the movable unit when the movable unit reaches the start of the braking zone to couple the two units together. The movable unit acts to push the brake unit through the braking zone such that movement of the magnets of the brake unit relative to the conductive material induces eddy currents in the conductive material to create a braking force between the brake unit and the plate of conductive material to brake the brake unit and the movable unit. In an alternative arrangement, the magnets are installed directly in the movable unit to eliminate the separate brake unit.

Abstract: Start-up circuit for current mirror circuits to facilitate transition from a zero-current state to an operation state. The start-up circuit includes two sets of current control devices. A set is coupled to each leg of the current mirrored circuit to provide a bias on start-up. The current control devices are coupled together to mirror the current that continues during the operational state such that the start-up circuit in combination with the operating circuit do not draw more current in the operational state than the operating circuit would normally draw in the operational state.

Abstract: According to one embodiment, an integrated circuit (IC) is disclosed. The IC includes a package, a die mounted within the package, circuit components mounted on the die, and a voltage regulator mounted on the die to supply power to the circuit components.

Abstract: Circuitry for controlling the oscillation frequency of an oscillator by using a digitally tunable on-chip capacitor bank. The capacitor bank includes a plurality of on-chip capacitors, each of which is independently selectable by a control signal for providing a selectable amount of capacitance to the oscillator to control the oscillator's oscillation frequency.

Abstract: An apparatus and method manufactures biodegradable food dishes and the like using a slurry of food starch and limestone which is formed and heated in a press into a shape of a food dish or food container or the like. The formed dishes or containers are removed from the press and trimmed in a trimming station, after which a lamination station laminates a biodegradable film onto food contacting surfaces of the food dish or the like. An optional step of applying a wax coating to a rear surface of the food dish or the like is provided. The now completed food dish or food container is provided to a packaging apparatus for stacking and packaging.

Abstract: A system for suspending a structure from a tree comprising a collection of primary tension members interwoven to define a sleeve adapted to grip a portion of the tree, and at least one hanger assembly extending from the sleeve having an end connectable to the structure to be suspended. The suspension system accommodates different sizes of tree trunks and branches, and changes in diameter of the tree. The system of the present invention is mountable to a tree without damaging the tree or impeding its growth. The system accommodates the natural flexing of the tree due to wind while reliably retaining any supported structure suspended above the ground.

Abstract: According to an embodiment of the invention, a method and apparatus for dynamic reference voltage adjustment are described. According to one embodiment, a reference circuit comprises a reference node to provide a reference voltage; a first transistor device to receive a first configuration signal at a gate terminal, a current to flow through the first transistor device when the first configuration signal is a first value; and a second transistor device to receive a first voltage potential at a gate terminal, the current to flow through the second transistor device and the reference voltage to be increased by the first voltage potential when the configuration signal is a second value.

Abstract: According to one embodiment, an integrated circuit (IC) is disclosed. The IC includes a package, a die mounted within the package, circuit components mounted on the die, and a voltage regulator mounted on the die to supply power to the circuit components.

Abstract: According to an embodiment of the invention, a method and apparatus for dynamic reference voltage adjustment are described. According to one embodiment, a reference circuit comprises a reference node to provide a reference voltage; a first transistor device to receive a first configuration signal at a gate terminal, a current to flow through the first transistor device when the first configuration signal is a first value; and a second transistor device to receive a first voltage potential at a gate terminal, the current to flow through the second transistor device and the reference voltage to be increased by the first voltage potential when the configuration signal is a second value.

Abstract: An apparatus, in some embodiments, includes a first circuit to monitor a current, a second circuit to produce a reference current, and a control circuit coupled to the first circuit and the second circuit. In operation, the control circuit processes a first signal received from the first circuit and a second signal received from the second circuit and provides a control signal to the circuit to control the current. A method, in some embodiments, includes generating a reference current, generating a first current in a circuit, generating a second current related to the first current, and reducing the first current when the second current is greater than the reference current.