Patents by Inventor Robert G. Fleck
Robert G. Fleck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9619606Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).Type: GrantFiled: March 31, 2014Date of Patent: April 11, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Scott R. Summerfelt, Robert G. Fleck
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Patent number: 8883629Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).Type: GrantFiled: September 16, 2010Date of Patent: November 11, 2014Assignee: Texas Instruments IncorporatedInventors: Scott R. Summerfelt, Robert G. Fleck
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Publication number: 20140308762Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the subregion (208).Type: ApplicationFiled: June 26, 2014Publication date: October 16, 2014Inventors: Scott R. Summerfelt, Robert G. Fleck
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Publication number: 20140215425Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: Texas Instruments IncorporatedInventors: Scott R. Summerfelt, Robert G. Fleck
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Publication number: 20110004859Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).Type: ApplicationFiled: September 16, 2010Publication date: January 6, 2011Applicant: Texas Instruments IncorporatedInventors: Scott R. Summerfelt, Robert G. Fleck
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Patent number: 7759182Abstract: Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, but where whole dummy active areas can not be accommodated. The dummy active areas are staggered so as to provide uniform parasitic capacitive coupling to overlying leads regardless of the placement of the leads. The dummy active areas are substantially evenly separated from one another by dividers. The dummy active areas and dividers are formed concurrently with formation of semiconductor devices in non-dummy active areas. The dummy active areas mitigate yield loss by, among other things, providing more uniformity across the substrate, at least with regard to parasitic capacitances and stress and subsequent processing.Type: GrantFiled: November 8, 2006Date of Patent: July 20, 2010Assignee: Texas Instruments IncorporatedInventors: Robert G. Fleck, Leif C. Olsen, Howard L. Tigelaar
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Publication number: 20100041232Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).Type: ApplicationFiled: July 21, 2009Publication date: February 18, 2010Inventors: Scott R. Summerfelt, Robert G. Fleck
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Publication number: 20080122009Abstract: Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, but where whole dummy active areas can not be accommodated. The dummy active areas are staggered so as to provide uniform parasitic capacitive coupling to overlying leads regardless of the placement of the leads. The dummy active areas are substantially evenly separated from one another by dividers. The dummy active areas and dividers are formed concurrently with formation of semiconductor devices in non-dummy active areas. The dummy active areas mitigate yield loss by, among other things, providing more uniformity across the substrate, at least with regard to parasitic capacitances and stress and subsequent processing.Type: ApplicationFiled: November 8, 2006Publication date: May 29, 2008Inventors: Robert G. Fleck, Leif C. Olsen, Howard L. Tigelaar
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Patent number: 4852083Abstract: A digital crossbar switch for switching data from an input/output data bus to an internal data bus and to the same or another input/output data bus which includes a plurality of multiplexer logic units, an m-bit internal data bus coupled to each of said multiplexer logic units where m is an integer, and a plurality of n-bit input/output data buses one connected to each of the multiplexer logic units were n is an integer. The switch further includes an m/n to 1 multiplexer, where m/n is an integer, in each multiplexer logic unit. The m/n to 1 multiplexer has an input control to the internal data bus and an output coupled to a corresponding one of the input/output data buses and is operative in response to a configuration control signal to switch a selected n-bits of data from the internal data bus to the corresponding input/output data bus. A memory storage for storing configuration control signals is coupled to the m/n to 1 multiplexer.Type: GrantFiled: June 22, 1987Date of Patent: July 25, 1989Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Niehaus, Robert G. Fleck, Stephen Li, Bob D. Strong