Adjustable dummy fill
A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).
This application claims the benefit under 35 U.S.C. § 119(e) of Provisional Appl. No. 61/088,212, filed Aug. 12, 2008, and to Provisional Appl. No. 61/091,937, filed Aug. 26, 2008, which are incorporated herein by reference in their entirety.
BACKGROUND OF THE INVENTIONEmbodiments of the present invention relate to calculation and placement of an adjustable dummy fill layer to improve semiconductor integrated circuit processing.
Shrinking semiconductor integrated circuit feature sizes have placed increasing challenges on semiconductor integrated circuit processing. In particular, a balance between high packing density and yield require a finely tuned manufacturing process. Second order effects that might have been ignored a decade ago are now critical to cost-effective processing as will be explained in detail.
The ferroelectric capacitor 104 is a composite stack formed in layers and etched with a single mask step. The lower plate 140 is preferably formed of titanium aluminum nitride (TiAlN) in conductive contact with iridium layer 142. Likewise, the upper plate 148 is preferably formed of titanium aluminum nitride (TiAlN) in conductive contact with iridium layer 146. The upper and lower plates are separated by ferroelectric layer 144. The ferroelectric layer 144 is preferably formed of lead zirconate titanate (PZT) or strontium bismuth tantalite (SBT). A second dielectric region 160 overlies the ferroelectric capacitor 104. Plate voltage lead (MET1) 150 is formed on this second dielectric region and connected to the top plate 148 of the ferroelectric capacitor 104 by a first via region (VIA0). In areas of the semiconductor memory where there are no memory cells, VIA0 may directly contact CONT to electrically connect MET1 to underlying gate or source/drain regions.
A significant problem disclosed in the prior art involves re-deposition of noble metal components (e.g. Pt, Pd, Ag, Au, Ir) on the sidewalls of the ferroelectric capacitor 104 during plasma etch. Such re-deposition may cause the ferroelectric capacitor to leak or even completely short the upper and lower plates, thereby reducing the overall yield of the semiconductor memory device. The prior art discloses a significant yield improvement is possible by controlling the sidewall slope of the ferroelectric capacitor to a range of 78° to 88° with respect to the surface of dielectric layer 130. This sidewall slope advantageously reduces the re-deposition of noble metal components without a significant reduction of area of the ferroelectric capacitor 104. The present inventors have discovered other factors that influence re-deposition of noble metal components on sidewalls of the ferroelectric capacitor 104 as will be discussed in detail. There is therefore a need to further improve the method of forming ferroelectric capacitors.
BRIEF SUMMARY OF THE INVENTIONIn a preferred embodiment of the present invention, a method of placing a dummy fill layer on a substrate is disclosed. The method includes identifying a sub-region of the substrate. A density of a layer in the sub-region is determined. A pattern of a dummy fill layer is selected to produce a predetermined density of the layer in the sub-region. The dummy fill layer pattern is then placed in the sub-region. Local dummy layer fill patterns in a sub-region may be varied based on global density to achieve a repeatable overall density through an iterative procedure. The resulting uniform and repeatable layer density improves local uniformity and device to device repeatability of a density dependent semiconductor process.
The preferred embodiments of the present invention provide significant advantages in plasma etch stability for a given process over multiple designs as will become evident from the following detailed description.
The present inventors have determined that different designs using the same process flow may have significantly different yields. A primary reason for this anomaly is the different layer densities on different designs. In particular, the ferroelectric capacitor 104 of the memory cell (
In the following discussion it should be understood that formation of the dummy layer fill pattern on a substrate refers to the pattern on the processing reticle as well as to the semiconductor substrate which subsequently receives the pattern. Moreover, it should be understood that a drawn layer is drawn by a circuit designer. Alternatively, an extracted layer is generally formed at PG as a function of the drawn layer and may not be an electrically functional part of the circuit.
Turning now to
Step 210 of multi-step identification begins with a first sub-region and sequentially steps through all sub-regions. Referring now to
At step 216 a sub-region pattern density is selected. Although the fill pattern is arbitrary, the present inventors have selected square geometries having offset centers as represented at
When a sub-region includes an FeCAP drawn layer, it must also be included in the calculation. For example, if the sub-region includes an FeCAP drawn layer having a 20% density, the dummy layer fill pattern density is taken from the 20% row. If the BLOCK % is 15%, then 85% of the sub-region should receive a dummy layer pattern having a 19% density. This produces an FeCAP layer density in the sub-region of 0.85*19%+20% or 36.15%. Similarly, if the BLOCK % is 45%, then 55% of the sub-region should receive a dummy layer pattern having a 29% density. This produces an FeCAP layer density in the sub-region of 0.55*29%+20%=35.95%.
Recall that the BLOCK % and FECAP % densities from
In one embodiment of the present invention, global layer density starts at either a maximum or minimum value and the fill process is repeated with progressively lower or higher local density fill patterns, respectively, until the global density target is achieved.
In another embodiment, global layer density starts at an intermediate value that may be arbitrary or determined by calculation based on blocking area size. Various local fill pattern densities are then progressively either increased or decreased based on the corresponding global layer density variation until the final global layer density target is achieved. The resulting uniform density advantageously produces repeatable etch rates locally and globally for multiple designs and memory configurations. Overall yield is significantly improved.
The table of
Turning now to
Multi-step fill of remaining intermediate density blocking layer regions proceeds at step 704 as shown in detail at the right. A first sub-region is selected at step 710. As previously described with regard to
Referring now to
Multi-step fill of the super cells proceeds at step 802 as shown in detail at the right. A first super cell is selected at step 810. As previously described with regard to
Still further, while numerous examples have thus been provided, one skilled in the art should recognize that various modifications, substitutions, or alterations may be made to the described embodiments while still falling with the inventive scope as defined by the following claims. Moreover, although a preferred embodiment of the present invention employs the flow chart of
Claims
1. A method of placing a dummy fill layer on a substrate, comprising:
- a) identifying a sub-region of the substrate;
- b) determining a density of a layer in the sub-region;
- c) selecting a pattern of the dummy fill layer to produce a predetermined density; and
- d) placing the pattern of the dummy fill layer in the sub-region.
2. A method as in claim 1, comprising:
- e) partitioning the substrate into plural sub-regions including the sub-region;
- f) determining a density of the layer in each respective sub-region;
- g) selecting a respective pattern of the dummy fill layer to produce the predetermined density in each respective sub-region; and
- h) placing the respective pattern of the dummy fill layer in said each respective sub-region.
3. A method as in claim 2, comprising:
- selecting a global target layer density for the plural of sub-regions;
- determining if the dummy fill layer density of the plural sub-regions is within the global target layer density;
- selecting a new local target layer density for each of the plural of sub-regions and repeating steps (g) through (h) if the dummy fill layer density of the plural sub-regions is not within the global target layer density; and
- placing the respective pattern in said each respective sub-region of the plural sub-regions if the dummy fill layer density of the plural sub-regions is within the global target layer density.
4. A method as in claim 1, comprising:
- identifying a blocking area of the substrate; and
- identifying the sub-region of the substrate apart from the blocking area.
5. A method as in claim 1, wherein the predetermined density of each of the plural sub-regions is within 10 percent of the predetermined density of the sub-region.
6. A method as in claim 1, wherein the substrate is a reticle for producing a semiconductor device.
7. A method as in claim 1, wherein the substrate comprises a semiconductor device.
8. A method as in claim 1, wherein the layer comprises a capacitor.
9. A method as in claim 8, wherein the capacitor is a ferroelectric capacitor.
10. A method as in claim 1, wherein the layer comprises metal.
11. A method as in claim 1, wherein most of the substrate is filled with fixed dummy fill patterns.
12. A pattern of a composite layer of a semiconductor device, comprising:
- a drawn layer pattern having a first density; and
- an extracted layer pattern separate from the drawn layer pattern and having a second density,
- wherein the first density and the second density form a substantially uniform density of the pattern of the composite layer.
13. A pattern as in claim 12, comprising at least one blocking area of the pattern of the composite layer, wherein the extracted layer pattern is separate from the at least one blocking area.
14. A pattern as in claim 12, wherein the pattern of the composite layer is formed on a reticle for producing a semiconductor device.
15. A pattern as in claim 12, wherein the pattern of the composite layer is formed on a semiconductor device.
16. A pattern as in claim 12, wherein the composite layer comprises a capacitor.
17. A pattern as in claim 16, wherein the capacitor comprises a ferroelectric capacitor.
18. A pattern as in claim 12, wherein the composite layer comprises metal.
19. A method of placing a dummy fill layer on a substrate, comprising:
- identifying a plurality of sub-regions of the substrate;
- determining a density of a layer in each respective sub-region;
- selecting a first pattern of the dummy fill layer to place in a first of the plurality of sub-regions; and
- selecting a second pattern of the dummy fill layer to place in a second of the plurality of sub-regions.
20. A method as in claim 19, comprising:
- identifying a blocking area of the substrate; and
- identifying the sub-region of the substrate apart from the blocking area.
21. A method as in claim 19, comprising:
- partitioning the substrate into plural sub-regions including the first and second sub-region; and
- determining a density of the layer in each respective sub-region.
22. A method as in claim 19, wherein a final layer density of the first sub-region is within 10 percent of a final layer density of the second the sub-region.
23. A method as in claim 19, wherein the first pattern of the dummy fill layer is placed in the first of the plurality of sub-regions in a single step.
24. A method as in claim 19, wherein the second pattern is iteratively selected to produce a desired final layer density of the second sub-region.
25. A method of placing a dummy fill layer on a die, comprising:
- identifying a plurality of super cells of the die;
- determining a density of a layer in each respective super cell;
- selecting a first pattern of the dummy fill layer to place in a first super cell of the plurality of super cells; and
- selecting a second pattern of the dummy fill layer to place in a second of the plurality of super cells.
26. A method as in claim 25, comprising:
- identifying a blocking area of the super cell; and
- identifying the sub-region of the super cell apart from the blocking area.
27. A method as in claim 25, wherein a final layer density of the first super cell is within 10 percent of a final layer density of the second the super cell.
28. A method as in claim 25, wherein the second pattern is iteratively selected to produce a desired final layer density of the second super cell.
29. A method as in claim 28, wherein the second super cell is placed a plurality of times with the desired final layer density.
30. A method as in claim 25, wherein the at least one of the super cells comprises repeated cells, and wherein the dummy fill layer pattern is placed in each of the repeated cells.
31. A method as in claim 29, wherein the dummy fill layer pattern is placed in one of the repeated cells and repeated with each subsequent placement of said one of the repeated cells.
Type: Application
Filed: Jul 21, 2009
Publication Date: Feb 18, 2010
Inventors: Scott R. Summerfelt (Garland, TX), Robert G. Fleck (Allen, TX)
Application Number: 12/460,602
International Classification: H01L 21/3205 (20060101); H01L 21/02 (20060101);