Abstract: A semiconductor device includes a passive device region having a first source/drain region, a second source/drain region, a frontside contact over the first source/drain region, a backside contact below the second source/drain region, and a bonding oxide bonding the first source/drain region and the second source/drain region to a backside interlayer dielectric.

Abstract: A semiconductor device can include a passive device, having a top device including a top doped region, a top gate region, and a frontside contact, a bottom device including a bottom doped region, a bottom gate region, and a backside contact.

Abstract: A semiconductor device can include a passive device, having a passive device having a top device including a first top doped region and a second top doped region separated by a top gate region, and a first frontside contact and a second frontside contact over the first top doped region and the second top doped region, respectively, and a bottom device including a first bottom doped region and second bottom doped region separated by a bottom gate region, and a first backside contact and a second backside contact below the first bottom doped region and the second bottom doped region, respectively, a first well region and a second well region electrically connecting the top device to the bottom device.

Abstract: A semiconductor device can include a top device, a bottom passive device, and a first well region and a second well region adjacent to each other and separating the top device from the bottom passive device.

Abstract: A semiconductor device includes a silicon controlled rectifier (SCR) including a P-type doped region and an N-type doped region, an N-well region, a P-well region adjacent to the N-well region, a set of shallow trench isolation (STI) below the P-type doped region and the N-type doped region and within the N-well region and the P-well region, and a transistor coupled to the SCR.

Abstract: A semiconductor device includes a passive device including a first backside contact on a first side of the passive device, a second backside contact on a second side of the passive device, a first doped region over the first backside contact and on a backside of the passive device, a second doped region over the second backside contact and located on the backside of the passive device, a first well region over the first doped region, a second well region over the second doped region and a shallow trench isolation (STI) above the first well region and the second well region.

Abstract: A semiconductor device includes a base including a base contact, an emitter including an emitter contact, a well region below the base and the emitter, an extrinsic base between the base and the well region, and a collector located below the well region and on a backside of the semiconductor device. The base contact and the emitter contact are connected to a frontside of the semiconductor device.

Abstract: A semiconductor device includes a p-n junction including a P-type doped region and an N-typed doped region, an N-well region, a P-well region. The p-n junction is located between the N-well region and the P-well region. The semiconductor device further includes a set of shallow trench isolation (STI) below the p-n junction, the N-well region and the P-well region. There is no STI between an anode region and a cathode region of the p-n junction.

Abstract: A semiconductor device includes a first diode including a first well region, and a first doped region fenced by the first well region, a second diode including a second well region fencing the first well region, and a second doped region fenced by the second well region, and a silicon controlled rectifier (SCR) coupled to the set of diodes.

Abstract: An electrical antifuse bit cell structure includes a silicon controlled rectifier (SCR) having an anode, a cathode, and a blow gate. The blow gate is a Positive Field Effect Transistor (PFET) having a supply node for connection in series between a voltage supply and the anode of the SCR. The blow gate PFET in an on-state provides a permanent conductive path from the anode to the cathode.

Abstract: A semiconductor device includes a base including a first doped region, a second doped region and a plurality of nanosheet gates, a collector including a third doped region, and an emitter including a fourth doped region. The plurality of nanosheet gates is configured to control a resistance of the base.

Abstract: A semiconductor device includes a passive device including a first backside contact on a first side of the passive device, a second backside contract on a second side of the passive device, a spacer liner over sidewalls of the first backside contact and the second backside contact, and a shallow trench isolation (STI) above the first backside contact and the second backside contact and partially covering a top surface of the first backside contact and the second backside contact. The spacer liner is configured to prevent carrier transportation from the passive device.

Abstract: A semiconductor device includes a guardring including a first doped region and a first contact over the first doped region, a base including a second doped region and a second contact over the second doped region, a collector including a third doped region and a third contact over the third doped region, and an emitter including a fourth doped region and a fourth contact over the fourth doped region. The emitter, the collector, the base, and the guardring are separated on a backside of the semiconductor device via shallow trench isolation (STI) or floating gates.

Abstract: A semiconductor device includes a base including a first doped region and a first contact over the first doped region, a collector including a second doped region and a second contact over the second doped region, and an emitter including a third doped region and a third contact over the third doped region. The emitter, the collector, and the base are separated on a backside of the semiconductor device via one or more floating gates.

Abstract: An electrostatic discharge (ESD) protection diode in a semiconductor integrated circuit (IC) includes a silicon wafer. The IC includes a well region within the silicon wafer. The IC includes an N+ region and a P+ region within the well region. The IC includes a gate dielectric layer on top of the silicon wafer. The IC includes a floating gate layer on top of the gate dielectric layer. The IC includes an ovonic threshold switching (OTS) layer on top of the floating gate layer. The IC includes an interlayer dielectric (ILD) on top of the OTS layer.

Abstract: A semiconductor device can include a backside contact over a backside power delivery network (BSPDN), a first doped region over the backside contact, a well region over the first doped region, a second doped region over the well region, and gate regions surrounding the well region.

Abstract: A semiconductor device includes a passive device including a passive device including a first backside contact, a shallow trench isolation (STI) above the first backside contact and covering a top surface and an upper half of sidewalls of the first backside contact, and an interconnection layer covering a bottom surface of the first backside contact.

Abstract: A semiconductor device is provided and includes a device finger including field effect transistors (FETs) or bipolar junctions arrayed along a substrate and one or more implanted ballasting elements. Each of the one or more implanted ballasting elements contacts a collector or an emitter of one of the FETs or the bipolar junctions and extends substantially horizontally from the collector or the emitter of the one of the FETs or the bipolar junctions and through the substrate.

Abstract: A semiconductor device is provided including a backside deep trench capacitor present in a deep trench device region and electrically connected to a source/drain region of a transistor and to a backside back-end-of-the-line (BEOL) structure. In some embodiments, the semiconductor device can also include a logic device region including at least one logic transistor that is located adjacent to the deep trench device region.

Abstract: A semiconductor device includes a backside contact, a shallow trench isolation (STI), and a backside dielectric trench isolation (BDTI) below the STI. A top surface of the BDTI is connected to the STI on a backside of a high voltage region of the semiconductor device, a bottom surface of the BDTI is connected to a backside power interconnect, and the BDTI isolates a backside contact from a substrate.