Abstract: A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.

Abstract: A method of producing a synthesis gas which contains hydrogen and carbon dioxide. A hydrocarbon mioxture is pre-reformed to create a first mixture. The first mixture is then reformed in a catalytic ceramic membrane reactor (RCMC) with oxidizing an oxidizing mixture to form a raw synthesis gas. The oxidizing mixture contains oxygen, and the raw synthesis gas contains hydrogen, carbon monoxide, carbon dioxide, water, and an oxygen depleted mixture. Several of the process streams are also preheated. The oxidizing mixture is brought to a temperature between 871° C. and 1300° C. prior to the formation of the raw synthesis gas.

Abstract: An ESD protection power clamp for suppressing ESD events. A clamping transistor having power source connections connected across the power supply terminals of an integrated circuit is connected to clamp the voltage during an ESD event. An RC timing circuit defines a time interval where ESD voltage for triggering the FET out of conduction. An inverter circuit connects the RC and timing circuit to the clamping FET. A dynamic feedback transistor is connected in series with one stage of the inverter and the power supply. During an ESD event, the feedback transistor delays the time for disabling the FET transistor, providing increased immunity against mistriggering of the clamping transistor, and forces the circuit to reset following the mistrigger event.

Abstract: An ESD NMOSFET, and a method for lowering a ESD NMOSFET trigger voltage. An ESD NMOSFET is configured in triple well CMOS architecture where the first well is separated from second and third wells by respective shallow well isolation regions. The first well is also separated from the substrate along the bottom by a conductive band region. A substrate contact is located outside of the first, second and third wells, and provides a current path during an ESD event from the first well. Source and drain regions are formed in the first well, to form an FET with the drain being connected to an I/O pad which is subject to an ESD event. A resistive path extends through an opening in the conductive band region to a substrate contact, providing an increased I/O pad to substrate resistance which decreases the trigger voltage for the ESD NMOSFET.

Abstract: A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, the plurality of diffusion regions separated by a diode junction, wherein the implanting aligns an upper surface of the diode junction with the protective structure; and removing the protective structure. The method further comprises forming a silicide layer over the diffusion regions and aligned with the protective structure. The protective structure comprises a hard mask, wherein the hard mask comprises a silicon nitride layer. Alternatively, the protective structure comprises a polysilicon gate and insulating spacers on opposite sides of the gate. Furthermore, in the removing step, the spacers remain on the substrate.

Abstract: An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.

Abstract: The log positioning and conveying apparatus is used for conveying a log from an upstream end to a downstream end, and for positioning a log according to a predetermined downstream position. The apparatus comprises an open frame and a number of powered conveying rollers arranged therein in a row. These rollers, in addition to being rotatable, are displaceable in two directions relative to the open frame, namely, in a vertical direction for correcting the position of the log vertically relative to the open frame, and in a horizontal direction transversal to the longitudinal axis of the conveying apparatus, for correcting the position of the log transversely relative to the longitudinal axis.

Abstract: A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI.

Abstract: A method and structure for protection against latch-up is provided. Integrated circuits manufactured in accordance with the present disclosure feature well and substrate contacts of varying periodicity. Such a strategy enables maximizing the design of an integrated circuit as to the suppression of latch-up while concurrently optimizing available area on the chip allocable to circuit design. This method and structure is particularly beneficial to protect against cable discharge events and other discharge occurrences prone to injecting large current densities into an integrated circuit.

Abstract: An ESD protection circuit including the following: one or more inverters (I1, I2, I3), each of the one or more inverters having an input and an output; an RC network (11) having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N3) joined with the output of at least one of one or more inverters (I1, I2, I3); and a feedback device (NKP) in communication with clamping device (N3) and output node (RCT) of RC network (11). An ESD protection circuit according to claim 7, wherein said RC network includes one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I1, I2, I3) includes a PFET and NFET pair (P0/N0, P1/N1, P2/N2).

Abstract: A method and apparatus for protection against electrostatic discharge (ESD) with improved latch-up robustness featuring a silicide blocked p-type field effect transistor is disclosed. The transistor has a snapback voltage that is less than the breakdown voltage of its gate oxide. The transistor is part of an integrated circuit and coupled to an I/O pad having no n-diffusions connected directly to it. A given integrated circuit may employ one or more the transistors configured in accordance with the invention that are associated with one or more I/O pads within the integrated circuit.

Abstract: The log positioning and conveying apparatus is used for conveying a log from an upstream end to a downstream end, and for positioning a log according to a predetermined downstream position. The apparatus comprises an open frame and a number of powered conveying rollers arranged therein in a row. These rollers, in addition to being rotatable, are displaceable in two directions relative to the open frame, namely, in a vertical direction for correcting the position of the log vertically relative to the open frame, and in a horizontal direction transversal to the longitudinal axis of the conveying apparatus, for correcting the position of the log transversely relative to the longitudinal axis.

Abstract: In an integrated process for the production of synthesis gas, a partial oxidation unit (1) and a steam methane reformer (2) are used to convert natural gas or another fuel to first and second mixtures (11, 12) of at least carbon monoxide and hydrogen, only the first process consuming oxygen. Carbon dioxide (15, 25) derived from the second mixture is sent to the inlet of the first process to reduce the oxygen consumption.

Abstract: A high speed turbine includes a bearing cartridge which may easily be replaced with another cartridge capable of delivering different torque capacities and/or speeds of revolution of a rotor assembly. The rotor assembly comprises a rotor disc secured to a rotor shaft, and is supported by bearing within the cartridge.