Abstract: A structure capable of effectively preventing dopant diffusion from source/drain regions into an underlying semiconductor-on-insulator (SOI) layer of fully-depleted SOI transistors with U-shaped channels is provided. By inserting a dopant diffusion barrier layer between an SOI layer of an SOI substrate and a doped extension layer from which source/drain extension regions are derived, the undesired dopant diffusion from the source/drain extension regions into the underlying SOI layer can be prevented.

Abstract: The present invention provides for a method of fabricating a semiconductor device, the method includes depositing a nitride layer on an ETSOI layer; forming a dummy gate over the nitride layer; forming nitride gate spacers from the nitride layer; growing a sacrificial layer on the ETSOI layer, the sacrificial layer composing a material that can be at least partially converted to a metal layer by a metal-bearing gas; forming refractory metal contacts using the sacrificial layer and a consumptive process; depositing an oxide protect layer on the refractory metal contacts; removing the dummy gate using a mask and etch process combined with chemical-mechanical polishing (CMP); etching the ETSOI layer to form a U-shaped channel; and depositing the final gate stack into the U-shaped channel.

Abstract: The present invention provides for a method of fabricating a semiconductor device, the method includes depositing a nitride layer on an ETSOI layer; forming a dummy gate over the nitride layer; forming nitride gate spacers from the nitride layer; growing a sacrificial layer on the ETSOI layer, the sacrificial layer composing a material that can be at least partially converted to a metal layer by a metal-bearing gas; forming refractory metal contacts using the sacrificial layer and a consumptive process; depositing an oxide protect layer on the refractory metal contacts; removing the dummy gate using a mask and etch process combined with chemical-mechanical polishing (CMP); etching the ETSOI layer to form a U-shaped channel; and depositing the final gate stack into the U-shaped channel.

Abstract: A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.

Abstract: A structure capable of effectively preventing dopant diffusion from source/drain regions into an underlying semiconductor-on-insulator (SOI) layer of fully-depleted SOI transistors with U-shaped channels is provided. By inserting a dopant diffusion barrier layer between an SOI layer of an SOI substrate and a doped extension layer from which source/drain extension regions are derived, the undesired dopant diffusion from the source/drain extension regions into the underlying SOI layer can be prevented.

Abstract: A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.

Abstract: A structure capable of effectively preventing dopant diffusion from source/drain regions into an underlying semiconductor-on-insulator (SOI) layer of fully-depleted SOI transistors with U-shaped channels is provided. By inserting a dopant diffusion barrier layer between an SOI layer of an SOI substrate and a doped extension layer from which source/drain extension regions are derived, the undesired dopant diffusion from the source/drain extension regions into the underlying SOI layer can be prevented.

Abstract: In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

Abstract: A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.

Abstract: A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.

Abstract: A structure capable of effectively preventing dopant diffusion from source/drain regions into an underlying semiconductor-on-insulator (SOI) layer of fully-depleted SOI transistors with U-shaped channels is provided. By inserting a dopant diffusion barrier layer between an SOI layer of an SOI substrate and a doped extension layer from which source/drain extension regions are derived, the undesired dopant diffusion from the source/drain extension regions into the underlying SOI layer can be prevented.

Abstract: A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a gate structure formed on the channel region. A first dual-layer source/drain region is on the first active region and a second dual-layer source/drain region is on the second active region. The first and second dual-layer source/drain regions include stacked layers formed of different semiconductor materials. A first extension region is embedded in the first active region and a second extension region is embedded in the second active region.

Abstract: A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a gate structure formed on the channel region. A first dual-layer source/drain region is on the first active region and a second dual-layer source/drain region is on the second active region. The first and second dual-layer source/drain regions include stacked layers formed of different semiconductor materials. A first extension region is embedded in the first active region and a second extension region is embedded in the second active region.

Abstract: A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that serve as channel regions of the device; forming spacers and doped source/drain regions in the SOI layer on opposite sides of the dummy gates; depositing a gap fill dielectric; removing the dummy gates/gate oxide; recessing areas of the SOI layer exposed by removal of the dummy gates forming one or more u-shaped grooves that extend part-way through the SOI layer such that a thickness of the SOI layer remaining in the channel regions is less than a thickness of the SOI layer in the doped source/drain regions under the spacers; and forming u-shaped replacement gate stacks in the u-shaped grooves such that u-shaped channels are formed in fully depleted regions of the SOI layer adjacent to the u-shaped replacement gate stacks.

Abstract: In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.

Abstract: A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that serve as channel regions of the device; forming spacers and doped source/drain regions in the SOI layer on opposite sides of the dummy gates; depositing a gap fill dielectric; removing the dummy gates/gate oxide; recessing areas of the SOI layer exposed by removal of the dummy gates forming one or more u-shaped grooves that extend part-way through the SOI layer such that a thickness of the SOI layer remaining in the channel regions is less than a thickness of the SOI layer in the doped source/drain regions under the spacers; and forming u-shaped replacement gate stacks in the u-shaped grooves such that u-shaped channels are formed in fully depleted regions of the SOI layer adjacent to the u-shaped replacement gate stacks.

Abstract: In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

Abstract: A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a gate structure formed on the channel region. A first dual-layer source/drain region is on the first active region and a second dual-layer source/drain region is on the second active region. The first and second dual-layer source/drain regions include stacked layers formed of different semiconductor materials. A first extension region is embedded in the first active region and a second extension region is embedded in the second active region.

Abstract: A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a gate structure formed on the channel region. A first dual-layer source/drain region is on the first active region and a second dual-layer source/drain region is on the second active region. The first and second dual-layer source/drain regions include stacked layers formed of different semiconductor materials. A first extension region is embedded in the first active region and a second extension region is embedded in the second active region.